Datasheet

TVP5158, TVP5157, TVP5156
www.ti.com SLES243G –JULY 2009–REVISED APRIL 2013
Table 2-1. Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
Analog Section
VIN_1_P 108 I Analog video input for ADC channel 1.
VIN_1_N 109 I Common-mode reference input for ADC channel 1.
VIN_2_P 112 I Analog video input for ADC channel 2.
VIN_2_N 113 I Common-mode reference input for ADC channel 2.
VIN_3_P 121 I Analog video input for ADC channel 3.
VIN_3_N 122 I Common-mode reference input for ADC channel 3.
VIN_4_P 125 I Analog video input for ADC channel 4.
VIN_4_N 126 I Common-mode reference input for ADC channels.
REXT_2K 116 I External resistor for AFE bias generator. Connect external 1.8kΩ resistor to ground.
AIN_1 95 I Analog audio input for channel 1 (No Connect for TVP5156 Only)
AIN_2 94 I Analog audio input for channel 2 (No Connect for TVP5156 Only)
AIN_3 93 I Analog audio input for channel 3 (No Connect for TVP5156 Only)
AIN_4 92 I Analog audio input for channel 4 (No Connect for TVP5156 Only)
External clock reference input. It may be connected to external oscillator with 1.8-V compatible
XTAL_IN 99 I
clock signal or 27.0-MHz crystal oscillator.
XTAL_REF 100 G Crystal reference. Connected to analog ground internally.
External clock reference output. Not connected if XTAL_IN is driven by an external single-
XTAL_OUT 101 O
ended oscillator.
Analog Power
VDDA_1_1 103, 106, 119 P 1.1-V analog supply
91, 102, 107,
VDDA_1_8 114, 115, 120, P 1.8-V analog supply
127
VDDA_3_3 128 P 3.3-V analog supply for all 4 video channels
96, 98, 104,
105, 110, 111,
VSSA G Analog ground
117, 118, 123,
124
Digital Power
1, 6, 12, 14, 20,
26, 33, 38, 47,
VSS 49, 55, 61, 65, G Digital ground
73, 79, 82, 87,
90
13, 18, 23, 32,
VDD_1_1 35, 44, 52, 64, P Digital core supply. Connect to 1.1-V digital supply.
67, 76, 84
15, 29, 41, 58,
VDD_3_3 P Digital I/O supply. Connect to 3.3-V digital supply.
70, 81
Digital Section
INTREQ 2 O Interrupt request. Interrupt signal to host processor.
RESETB 3 I Reset. An active low signal that controls the reset state.
SCL 4 I/O I
2
C serial clock (open drain)
SDA 5 I/O I
2
C serial data (open drain)
OSC_OUT 97 O Buffered crystal oscillator output. 1.8-V compatible.
OCLK_P 51 O Output data clock+. All four digital video output ports are synchronized to this clock.
Output data clock- for 2-Ch time-multiplexed mode or data clock input for 8-Ch video cascade
OCLK_N/CLKIN 50 I/O
mode
68, 69, 71, 72,
DVO_A_[7:0] O Digital video output data bus.
74, 75, 77, 78
Copyright © 2009–2013, Texas Instruments Incorporated Terminal Assignments 13
Submit Documentation Feedback
Product Folder Links: TVP5158 TVP5157 TVP5156