Datasheet

TVP5158, TVP5157, TVP5156
SLES243G –JULY 2009–REVISED APRIL 2013 www.ti.com
REVISION COMMENTS
SLES243E Table 4-1, Added RAM version MSB and LSB registers (subaddress: 05h-06h).
Table 4-6, Added RAM version MSB register (subaddress: 05h).
Table 4-7, Added RAM version LSB register (subaddress: 06h).
Section 5.1, Updated V
ESD
limits.
SLES243F Table 3-11, Super-frame format and timing information modified.
Table 3-10, 6-Ch Half-D1, 6-Ch Half-D1 + 1-Ch D1 and 3-Ch D1 formats added
Table 3-12, Added BOP and EOP bits.
Table 3-13, Added definitions for BOP and EOP bits.
Table 4-1, Changed default setting for I
2
C register AEh from 00h to 01h.
Table 4-1, Corrected register name for I
2
C register 06h.
Table 4-43, Definitions for bits 7 and 3 of I
2
C register 60h added.
Table 4-52, Output timing delay control range modified.
Table 4-54, Register settings for several different screen colors provided.
Table 4-63, YCbCr output code range modified.
Table 4-67, Embedded sync offset control range modified.
Table 4-69, Definition for bit 7 of I
2
C register B1h modified.
Table 4-70, Definition for bit 7 of I
2
C register B2h added.
Table 4-75, Definition for bits 7:5 of I
2
C register B9h added.
Table 4-77, 11.025kHz, 12kHz, 22.05kHz and 24kHz audio sample rates added.
Table 4-82, Definition for bits 3:0 of I
2
C register C5h modified.
Table 4-91, Definition for bits 5:0 of I
2
C register F2h modified.
Table 4-92, Definition for bits 5:0 of I
2
C register F4h modified.
Table 4-93, Definition for bits 5:0 of I
2
C register F6h modified.
SLES243G Section 3.6, Changed I2C addresses shown for Noise Reduction registers
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