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11.6 I
2
C Host Port Timing
VC1
(SDA)
t1
t3
t7
t6
t8
t5
t2
t3
VC0
(SCL)
Data
Stop Start Stop
t4
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
PARAMETER TEST CONDITIONS MIN MAX UNIT
t
1
Bus free time, between STOP and START 1.3 µ s
t
2
Setup time, (repeated) START condition 0.6 µ s
t
3
Hold time, (repeated) START condition 0.6 µ s
t
4
Setup time, STOP condition 0.6 ns
t
5
Data setup time 100 ns
t
6
Data hold time 0 0.9 µ s
t
7
Rise time, VC1(SDA) and VC0(SCL) signal Specified by design 250 ns
t
8
Fall time, VC1(SDA) and VC0(SCL) signal Specified by design 250 ns
C
b
Capacitive load for each bus line Specified by design 400 pF
f
I2C
I
2
C clock frequency 400 kHz
Figure 11-4. I
2
C Host Port Timing
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