Datasheet
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4 Functional Description
4.1 Analog Front End
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
TERMINAL
I/O DESCRIPTION
NAME NO.
HSYNC1 100 O Horizontal synchronization
HSYNC2 77
HSYNC3 58
HSYNC4 39
VSYNC1 /PALI1 95 O 1. VSYNC: Vertical synchronization
VSYNC2 /PALI2 76 2. PALI: PAL line indicator or horizontal lock indicator. For the PAL line indicator, a 1
VSYNC3 /PALI3 57 indicates a noninverted line, and a 0 indicates an inverted line.
VSYNC4 /PALI4 38
PDN 122 I Power down (active low). A 0 on this pin puts the decoder in standby mode. PDN preserves
the value of the registers.
RESETB 121 I Active-low reset. RESETB can be used only when PDN = 1. When RESETB is pulled low, it
resets all the registers and restarts the internal microprocessor.
SCL 120 I/O I
2
C serial clock (open drain)
SDA 119 I/O I
2
C serial data (open drain)
I2CA0 118 I During power-on reset, this pin is sampled along with pin 117 (I2CA1) to determine the I
2
C
address the device is configured to. A 10-k Ω resistor should pull this either high (to IOVDD)
or low to select different I
2
C device addresses.
I2CA1 117 I During power-on reset, this pin is sampled along with pin 118 (I2CA0) to determine the I
2
C
address the device is configured to. A 10-k Ω resistor should pull this either high (to IOVDD)
or low to select different I
2
C device addresses.
CLK1 103 O Unscaled system data clock at either 27 MHz or 54 MHz
CLK2 84
CLK3 61
CLK4 42
SCLK1 104 O Scaled system data clock at 27 MHz. This signal can be used to qualify scaled/unscaled
SCLK2 85 data when the unscaled system data clock is set to 54 MHz.
SCLK3 62
SCLK4 43
XIN/OSC 124 I External clock reference. The user may connect XIN to an oscillator or to one terminal of a
XOUT 123 O crystal oscillator. The user may connect XOUT to the other terminal of the crystal oscillator
or not connect XOUT at all. One single 14.31818-MHz crystal or oscillator is needed for
ITU-R BT.601 sampling, for all supported standards.
CH1_OUT[7:0] 105–112 O Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 1
CH2_OUT[7:0] 86–93 O Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 2
CH3_OUT[7:0] 67–74 O Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 3
CH4_OUT[7:0] 48–55 O Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 4
TMS 36 I Test-mode select. This pin should be connected to digital ground for correct device
operation.
Each channel of the TVP5154 decoder has an analog input channel that accepts two video inputs, which
should be ac coupled through 0.1- µ F capacitors. The decoder supports a maximum input voltage range of
0.75 V; therefore, an attenuation of one-half is needed for standard input signals with a peak-to-peak
variation of 1.5 V. The maximum parallel termination before the input to the device is 75 Ω . Refer to
schematic at the end of this document for recommended configuration. The two analog input ports can be
connected as follows:
• Two selectable composite video inputs or
• One S-video input
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level.
The programmable gain amplifier (PGA) and the automatic gain control (AGC) circuit work together to
ensure that the input signal is amplified or attenuated correctly, ensuring the proper input range for the
ADC.
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