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11.5 Timing Requirements
t3 t4
t6
t1 t2
Negative edge
clock
Positive edge
clock
Y/C & Syncs
Data 1 Data 2
t5
Unscaled Data 1 Unscaled Data 2Scaled Data 1 Scaled Data 2
t7
t8
t3 t4
t9 t9
Y/C & Syncs
CLK
SCLK
t1 t2
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
Duty cycle SCL 50 %
t
1
CLK high time (at 27 MHz) 13.5 ns
t
2
CLK low time (at 27 MHz) 13.5 ns
t
3
CLK fall time (at 27 MHz) 90% to 10% 5 ns
t
4
CLK rise time (at 27 MHz) 10% to 90% 5 ns
t
5
Output hold time 10 ns
t
6
Output delay time 25 ns
t
7
Output hold time 4 ns
t
8
Output delay time 16.5 ns
t
9
Data period 18.5 ns
t
10
Output hold time 4 ns
t
11
Output delay time 16.5 ns
t
12
Data period 18.5 ns
t
13
CLK high time (at 54 MHz) 3 ns
t
14
CLK low time (at 54 MHz) 3 ns
t
15
CLK fall time (at 54 MHz) 90% to 10% 6 ns
t
16
CLK rise time (at 54 MHz) 10% to 90% 6 ns
(1) Measured with a load of 15 pF for 27-MHz signals, 25 pF for 54-MHz signals. By design. Timing not production tested.
Figure 11-1. Output Modes 0 and 1: Clocks, Video Data, and Sync
Figure 11-2. Output Mode 2: Clocks, Video Data, and Sync
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