Datasheet

www.ti.com
9.2.67 FIFO Reset Register
9.2.68 Line Number Interrupt Register
9.2.69 Pixel Alignment Registers
9.2.70 FIFO Output Control Register
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
Address C9h
Default 00h
7 6 5 4 3 2 1 0
Any data
Writing any data to this register resets the FIFO and clears any data present in both the FIFO and the
VDP registers.
Address CAh
Default 00h
7 6 5 4 3 2 1 0
Field 1 enable Field 2 enable Line number
This register is programmed to trigger an interrupt when the video line number matches this value in bits 5:0. This interrupt must be enabled
at address C1h. The value of 0 or 1 does not generate an interrupt.
Field 1 enable:
0 = Disabled (default)
1 = Enabled
Field 2 enable:
0 = Disabled (default)
1 = Enabled
Line number: (default 00h)
Address CBh CCh
Default 4Eh 00h
Address 7 6 5 4 3 2 1 0
CBh Switch pixel [7:0]
CCh Reserved Switch pixel [9:8]
These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP
controller initiates the program from one line standard to the next line standard; for example, the previous
line of teletext to the next line of closed caption. This value must be set so that the switch occurs after the
previous transaction has cleared the delay in the VDP, but early enough to allow the new values to be
programmed before the current settings are required.
Address CDh
Default 01h
7 6 5 4 3 2 1 0
Reserved Host access enable
This register is programmed to allow I
2
C access to the FIFO or allowing all VDP data to go out the video port.
Host access enable:
0 = Output FIFO data to the video output Y[7:0]
1 = Allow I
2
C access to the FIFO data (default)
Internal Control Registers56 Submit Documentation Feedback