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9.2.30 Interrupt Configuration Register B
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
Software initialization occurred enable:
0 = Disabled (default)
1 = Enabled
Field rate changed:
0 = Disabled (default)
1 = Enabled
Line alternation changed:
0 = Disabled (default)
1 = Enabled
Color lock changed:
0 = Disabled (default)
1 = Enabled
H/V lock changed:
0 = Disabled (default)
1 = Enabled
TV/VCR changed:
0 = Disabled (default)
1 = Enabled
Interrupt enable register B is used by the external processor to mask unnecessary interrupt sources for
interrupt B. Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the
external pin. Conversely, bits loaded with 0s mask the corresponding interrupt condition from generating
an interrupt on the external pin. This register only affects the external pin; it does not affect the bits in the
interrupt status register. A given condition can set the appropriate bit in the status register and not cause
an interrupt on the external pin. To determine if this device is driving the interrupt pin, either AND interrupt
status register B with interrupt enable register B, or check the state of interrupt B in the interrupt B active
register.
Address 1Eh
Default 00h
7 6 5 4 3 2 1 0
Reserved Interrupt polarity B
Interrupt polarity B:
0 = Interrupt B is active low (default).
1 = Interrupt B is active high.
Interrupt polarity B must be same as interrupt polarity A bit at bit 0 of the interrupt configuration register A
at address C2h.
Interrupt configuration register B is used to configure the polarity of interrupt B on the external interrupt
pin. When the interrupt B is configured for active low, the pin is driven low when active and high
impedance when inactive (open drain). Conversely, when the interrupt B is configured for active high, it is
driven high for active and driven low for inactive.
Internal Control Registers40 Submit Documentation Feedback