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2 Functional Block Diagram
M
U
X
M
U
X
M
U
X
M
U
X
AIP1A
AIP1B
AIP2A
AIP2B
AIP3A
AIP3B
AIP4A
AIP4B
AGC
AGC
AGC
AGC
9−Bit
A/D
9−Bit
A/D
9−Bit
A/D
9−Bit
A/D
Y/C
SEPARATION
VBI SLICER
VBI SLICER
VBI SLICER
VBI SLICER
LUMINANCE
PROCESSING
LUMINANCE
PROCESSING
LUMINANCE
PROCESSING
LUMINANCE
PROCESSING
CHROMINANCE
PROCESSING
CHROMINANCE
PROCESSING
CHROMINANCE
PROCESSING
CHROMINANCE
PROCESSING
SCALER
SCALER
SCALER
SCALER
OUTPUT FORMATTEROUTPUT FORMATTEROUTPUT FORMATTEROUTPUT FORMATTER
CH1_OUT [7:0]
YC
B
C
R
8−Bit 4:2:2
CH2_OUT [7:0]
YC
B
C
R
8−Bit 4:2:2
CH3_OUT [7:0]
YC
B
C
R
8−Bit 4:2:2
CH4_OUT [7:0]
YC
B
C
R
8−Bit 4:2:2
SCL
SDA
XIN/OSC
XOUT
PLL
I2C
INTERFACE
HOST
PROCESSOR
SYNC PROCESSOR
FID/GLCO[1−4]
VSYNC/PAL[1−4]
INTERQ/GPCL/BLK[1−4]
HSYNC[1−4]
AVID[1−4]
CLK[1−4]
SCLK[1−4]
Y/C
SEPARATION
Y/C
SEPARATION
Y/C
SEPARATION
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
Figure 2-1. Functional Block Diagram
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