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9.2 Direct Register Definitions

9.2.1 Video Input Source Selection #1 Register

TVP5154

4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER

WITH INDEPENDENT SCALERS AND FAST LOCK

SLES163A – MARCH 2006 – REVISED JULY 2006

Table 9-1. Direct Register Summary (continued)

(1)

VDP configuration RAM data C3h B8h R/W

Configuration RAM address low byte C4h 1Fh R/W

Configuration RAM address high byte C5h 00h R/W

VDP status register C6h R

FIFO word count C7h R

FIFO interrupt threshold C8h 80h R/W

FIFO reset C9h 00h W

Line number interrupt CAh 00h R/W

Pixel alignment register low byte CBh 4Eh R/W

Pixel alignment register high byte CCh 00h R/W

FIFO output control CDh 01h R/W

Reserved CEh

Full field enable CFh 00h R/W

D0h 00h

Line mode registers R/W

D1h–FBh FFh

Full field mode register FCh 7Fh R/W

Reserved FDh

Decoder core write enables FEh 0Fh R/W

Decoder core read enables FFh 00h R/W

Direct registers are written to by performing a 3-byte I

C transaction:

START : DEVICE_ID : SUB_ADDRESS : DATA : STOP

Each direct register is eight bits wide.

Address 00h

Default 00h

7 6 5 4 3 2 1 0

Reserved Black output Reserved Channel n source selection S-video selection

Channel n source selection:

0 = AIPnA selected (default)

1 = AIPnB selected

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