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CLK
GLCO
23-Bit Frequency Control
Start Bit DCO Reset Bit
MSB
>128 CLK
1 CLK
7 CLK23 CLK
1 CLK
LSB
22 21
0
RTC
M
S
B
16 CLK
L
S
B
21
0
128 CLK
22-Bit Fsc Frequency Control
Start
Bit
Reset
Bit
2 CLK
1 CLK
2 CLK
3 CLK
1 CLK
PAL
Switch
44 CLK
GLCO Timing
8 Power-Up, Reset, and Power-Down Sequence (Required)
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
Figure 7-1. RTC Timing
Terminals 121 (RESETB) and 122 (PDN) work together to put the TVP5154 decoder into one of three
modes. Table 8-1 shows the configuration.
After power up, the device is in an unknown state with its outputs undefined until it receives a RESETB
active low for at least 200 ns. The power supplies should be active and stable for 10 ms before RESETB
becomes inactive. There are no power-sequencing requirements, except that all power supplies should
become active and stable within 500 ms of each other.
After each power-up and hardware reset, this procedure must be followed:
1. Wait at least 1 ms. Each decoder must be started by writing 0x00h to register 7Fh for all four decoders.
2. Wait at least 1 ms. Check the status of the TVP5154 by doing an I
2
C read of the version number,
register 81h, for all four decoders.
3. Verify that the value 0x54h is read.
4. If the value 0x54h is not read, toggle the TVP5154 reset pin (RESETB, pin number 121).
This procedure should be repeated if necessary until the value 0x54h is read from register 81h for all four
decoders.
Submit Documentation Feedback Power-Up, Reset, and Power-Down Sequence (Required) 19