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5.2.1 I
2
C Timing Requirements
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
Read Phase 1
abc
Step 1 0
I
2
C start (master) S
Step 2 7 6 5 4 3 2 1 0
I
2
C general address (master) 1 0 1 1 1 0 X 0
Step 3 9
I
2
C acknowledge (slave) A
Step 4 7 6 5 4 3 2 1 0
I
2
C read register address (master) addr addr addr addr addr addr addr addr
Step 5 9
I
2
C acknowledge (slave) A
Step 6 0
I
2
C stop (master) P
Read Phase 2
abc
Step 7 0
I
2
C start (master) S
Step 8 7 6 5 4 3 2 1 0
I
2
C general address (master) 1 0 1 1 1 0 X 1
Step 9 9
I
2
C acknowledge (slave) A
Step 10 7 6 5 4 3 2 1 0
I
2
C read data (slave) Data Data Data Data Data Data Data Data
Step 11
(1)
9
I
2
C not acknowledge (master) A
Step 12 0
I
2
C stop (master) P
(1) Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
The TVP5154 decoder requires delays in the I
2
C accesses to accommodate its internal processor’s timing.
In accordance with I
2
C specifications, the TVP5154 decoder holds the I
2
C clock line (SCL) low to indicate
the wait period to the I
2
C master. If the I
2
C master is not designed to check for the I
2
C clock line held-low
condition, the maximum delays must always be inserted where required. These delays are of variable
length; maximum delays are indicated in the following diagram:
Table 5-3. I
2
C Timing
Start Slave address (B8h) Ack Subaddress Ack Data (XXh) Ack Wait 128 µ s
(1)
Stop
(1) If the SCL pin is not monitored by the master to enable pausing, a delay of 128 µ s should be inserted between transactions for registers
00h through 8Fh.
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I
2
C Host Interface