Datasheet

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4.15 Clock and Data Control
Decoder
Scaler
Delay
54MHz
/2 =
27MHz
SCLK
CLK
Data
Mode
CLK edge
SCLK edge
00
01
Mode
=4
=1
=0
=2/3
!=3
=3
CLK OE
SCLK OE
Blank
=01
=11
=00
Field mode(0)
Field mode(1)
Field mode(2)
Field mode(3)
Field mode(4)
Field mode(5)
Field mode(6)
Field mode(7)
Field mode(8)
Field mode(9)
Field mode(10)
Field mode(11)
Field mode(12)
Field mode(13)
Field mode(14)
Field mode(15)
Decoder
Scaler
Delay
54MHz
/2 =
27MHz
SCLK
CLK
Data
Mode
CLK edge
SCLK edge
00
01
Mode
=4
=1
=0
=2/3
!=3
=3
CLK OE
SCLK OE
Blank
=01
=11
=00
Field mode(0)
Field mode(1)
Field mode(2)
Field mode(3)
Field mode(4)
Field mode(5)
Field mode(6)
Field mode(7)
Field mode(8)
Field mode(9)
Field mode(10)
Field mode(11)
Field mode(12)
Field mode(13)
Field mode(14)
Field mode(15)
TVP5154
4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER
WITH INDEPENDENT SCALERS AND FAST LOCK
SLES163A – MARCH 2006 – REVISED JULY 2006
Table 4-4. EAV and SAV Sequence
8-BIT DATA
D7 (MSB) D6 D5 D4 D3 D2 D1 D0
Preamble 1 1 1 1 1 1 1 1
Preamble 0 0 0 0 0 0 0 0
Preamble 0 0 0 0 0 0 0 0
Status word 1 F V H P3 P2 P1 P0
The status word may be modified in order to pass information about whether the current data corresponds
to scaled or unscaled data. See register 1Fh for more information.
Figure 4-4 shows a logical schematic of the data and clock control signals.
Figure 4-4. Clock and Data Control
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