Datasheet

Unscaled Data 1
Y/C & Syncs
CLK
Unscaled Data 2Scaled Data 1 Scaled Data 2
t
13
t
14
t
15
t
16
t
10
t
11
t
12
t
12
VC1
(SDA)
t1
t3
t7
t6
t8
t5
t2
t3
VC0
(SCL)
Data
Stop Start Stop
t4
TVP5154A
www.ti.com SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010
Figure 9-3. Output Mode 3: Clock, Video Data, and Sync (Positive Edge Clock)
9.6 I
2
C Host Port Timing
PARAMETER TEST CONDITIONS MIN MAX UNIT
t
1
Bus free time, between STOP and START 1.3 µs
t
2
Setup time, (repeated) START condition 0.6 µs
t
3
Hold time, (repeated) START condition 0.6 µs
t
4
Setup time, STOP condition 0.6 ns
t
5
Data setup time 100 ns
t
6
Data hold time 0 0.9 µs
t
7
Rise time, VC1(SDA) and VC0(SCL) signal Specified by design 250 ns
t
8
Fall time, VC1(SDA) and VC0(SCL) signal Specified by design 250 ns
C
b
Capacitive load for each bus line Specified by design 400 pF
f
I2C
I
2
C clock frequency 400 kHz
Figure 9-4. I
2
C Host Port Timing
9.7 Thermal Specifications
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
q
JA
Junction-to-ambient thermal resistance, still air Thermal pad soldered to 4-layer 17.17 °C/W
High-K PCB
q
JC
Junction-to-case thermal resistance, still air Thermal pad soldered to 4-layer 0.12 °C/W
High-K PCB
T
J(MAX)
Maximum junction temperature for reliable operation 105 °C
(1) The exposed thermal pad must be soldered to a JEDEC High-K PCB with adequate ground plane.
Copyright © 2007–2010, Texas Instruments Incorporated Electrical Specifications 85
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