Datasheet

Field 0 Field 1 Field 2 Field 3 Field 4 Field 0 Field 1Field 0 Field 1 Field 2 Field 3 Field 4 Field 0 Field 1

TVP5154A

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SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

8.4 Field Interleaving

In systems where either there are insufficient video ports on the back end processor to accommodate both

scaled and unscaled video streams, or where the back end processor does not have sufficient processing

power to perform compression on the unscaled image at the same time as other video processing, such

as composting of scaled images for display, it is possible to configure the TVP5154A to output different

image types on consecutive fields. In this configuration, the field rates for each of the scaled and unscaled

images is reduced to accommodate the interleaving of fields, while maintaining a 27-MHz pixel clock.

This is useful in video recording systems that are required to display a scaled image but still wish to

compress and store full resolution images, albeit at reduced field rates.

Field interleaving can generate a sequence of up to 16 fields, where each field can be either unscaled,

scaled, or blank.

8.4.1 Registers

The field loop count register controls how many fields are in the sequence. The field mode registers

control the output field type for each field.

Figure 8-3 shows how to configure field interleaving for a sequence of five fields where the first field is

unscaled, the second field is scaled, the third field is blank, the fourth field is scaled, and the fifth field is

blank.

Figure 8-3. Field Interleaving

Various additional registers exist to configure how the TVP5154A indicates to the back-end processor the

state of the current field. The Output Control register 1Fh allows the scaled/unscaled status to be indicated

by the upper bit of the SAV/EAV codes. The Output Control register 1Fh also allows the scaled/unscaled

status to be indicated by the DID codes of ancillary data.

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