Datasheet

TVP5154A

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

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7.2.79 Full Field Mode Register

Address FCh

Default 7Fh

7 6 5 4 3 2 1 0

Full field mode

This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual

line settings take priority over the full field register. This allows each VBI line to be programmed

independently but have the remaining lines in full field mode. The full field mode register has the same

definitions as the line mode registers (default 7Fh).

7.2.80 Decoder Write Enable Register

Address FEh

Default 0Fh

7 6 5 4 3 2 1 0

Reserved Decoder 4 Decoder 3 Decoder 2 Decoder 1

This register controls which of the four decoder cores receives I

C write transactions. A 1 in the

corresponding bit position enables the decoder to receive write commands.

Any combination of decoders can be configured to receive write commands, allowing all four decoders to

be programmed concurrently.

7.2.81 Decoder Read Enable Register

Address FFh

Default 00h

7 6 5 4 3 2 1 0

Reserved Decoder 4 Decoder 3 Decoder 2 Decoder 1

This register controls which of the four decoder cores responds to I

C read transactions. A 1 in the

corresponding bit position enables the decoder to respond to read commands.

If more than one decoder is enabled for reading, only the lowest numbered decoder responds. Reads from

multiple decoders at the same time is not possible.

Note that when register 0xFE is written to with any value, register 0xFF is set to 0x00. Likewise, when

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