Datasheet

TVP5154A
www.ti.com SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010
7.2.68 Interrupt Configuration Register A
Address C2h
Default 04h
7 6 5 4 3 2 1 0
Reserved YCbCr enable (VDPOE) Interrupt A Interrupt polarity A
YCbCr enable (VDPOE):
0 = YCbCr pins are high impedance.
1 = YCbCr pins are active if other conditions are met (default).
Interrupt A (read only):
0 = Interrupt A is not active on the external pin (default).
1 = Interrupt A is active on the external pin.
Interrupt polarity A:
0 = Interrupt A is active low (default).
1 = Interrupt A is active high.
Interrupt configuration register A is used to configure the polarity of the external interrupt terminal. When
interrupt A is configured as active low, the terminal is driven low when active and high impedance when
inactive (open collector). Conversely, when the terminal is configured as active high, it is driven high when
active and driven low when inactive.
7.2.69 VDP Configuration RAM Register
Address C3h C4h C5h
Default B8h 1Fh 00h
Address 7 6 5 4 3 2 1 0
C3h Configuration data
C4h RAM address (7:0)
C5h Reserved RAM address 8
The configuration RAM data is provided to initialize the VDP with initial constants. The configuration RAM
is 512 bytes organized as 32 different configurations of 16 bytes each. The first 12 configurations are
defined for the current VBI standards. An additional two configurations can be used as a custom
programmed mode for unique standards, such as Gemstar.
Address C3h is used to read or write to the RAM. The RAM internal address counter is automatically
incremented with each transaction. Addresses C5h and C4h make up a 9-bit address to load the internal
address counter with a specific start address. This can be used to write a subset of the RAM for only
those standards of interest. Registers D0h–FBh must all be programmed with FFh before writing or
reading the configuration RAM. Full field mode (CFh) must be disabled as well.
The suggested RAM contents are shown in Table 7-11. All values are hexadecimal.
Table 7-11. VBI Configuration RAM for Signals With Pedestal
INDEX ADDRESS 0 1 2 3 4 5 6 7 8 9 A B C D E F
WST SECAM 000 AA AA FF FF E7 2E 20 A6 E4 B4 0E 0 7 0 10 0
WST SECAM 010 AA AA FF FF E7 2E 20 A6 E4 B4 0E 0 7 0 10 0
WST PAL B 020 AA AA FF FF 27 2E 20 AB A4 72 10 0 7 0 10 0
WST PAL B 030 AA AA FF FF 27 2E 20 AB A4 72 10 0 7 0 10 0
WST PAL C 040 AA AA FF FF E7 2E 20 22 A4 98 0D 0 0 0 10 0
WST PAL C 050 AA AA FF FF E7 2E 20 22 A4 98 0D 0 0 0 10 0
WST NTSC 060 AA AA FF FF 27 2E 20 23 63 93 0D 0 0 0 10 0
WST NTSC 070 AA AA FF FF 27 2E 20 23 63 93 0D 0 0 0 10 0
NABTS, NTSC 080 AA AA FF FF E7 2E 20 A2 63 93 0D 0 7 0 15 0
Copyright © 2007–2010, Texas Instruments Incorporated Internal Control Registers 67
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