Datasheet

TVP5154A
SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010 www.ti.com
7.2.16 Configuration Shared Pins Register
Address 0Fh
Default 08h
7 6 5 4 3 2 1 0
Reserved FID PIN Reserved PALI PIN FID/GLCO VSYNC/PALI INTREQ/GPCL/VBLK CLK/PCLK
FID PIN function select:
0 = FID (default, if bit 3 is selected to output FID)
1 = Lock indicator (indicates whether the device is locked vertically)
PALI PIN function select:
0 = PALI (default, if bit 2 is selected to output PALI)
1 = Lock indicator (indicates whether the device is locked horizontally)
FID/GLCO function select (see register 03h, Section 7.2.4, for enhanced functionality):
0 = FID
1 = GLCO (default)
VSYNC/PALI function select (see register 03h, Section 7.2.4, for enhanced functionality):
0 = VSYNC (default)
1 = PALI
INTREQ/GPCL/VBLK function select:
0 = INTREQ (default)
1 = GPCL or VBLK depending on bit 7 of register 03h
CLK/PCLK (pins 42, 61, 84, 103) function select:
0 = CLK at 27 MHz (default)
1 = PCLK (1× pixel clock frequency at 13.5 MHz)
See Figure 7-1 for the relationship between the configuration shared pins.
7.2.17 Active Video Cropping Start Pixel MSB for Unscaled Data Register
Address 11h
Default 00h
7 6 5 4 3 2 1 0
AVID start pixel MSB [9:2]
Active video cropping start pixel MSB [9:2], set this register first before setting register 12h. The
TVP5154A decoder updates the AVID start values only when register 12h is written to. This start pixel
value is relative to the default values of the AVID start pixel.
38 Internal Control Registers Copyright © 2007–2010, Texas Instruments Incorporated
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