Datasheet

TVP5154A
SLES214CDECEMBER 2007REVISED SEPTEMBER 2010
www.ti.com
7.2.8 Luminance Processing Control #1 Register
Address 07h
Default 60h
7 6 5 4 3 2 1 0
2× luma output Pedestal not Disable raw Luma bypass enabled during vertical Luminance signal delay with respect to
enable present header blanking chrominance signal
2× luma output enable:
0 = Output depends on bit 4, luminance bypass enabled during vertical blanking (default).
1 = Outputs 2x luma samples during the entire frame. This bit takes precedence over bit 4.
Pedestal not present:
0 = 7.5 IRE pedestal is present on the analog video input signal.
1 = Pedestal is not present on the analog video input signal (default).
Disable raw header:
0 = Insert 656 ancillary headers for raw data
1 = Disable 656 ancillary headers and instead force dummy ones (0x40) (default)
Luminance bypass enabled during vertical blanking:
0 = Disabled. If bit 7, 2× luma output enable, is 0, normal luminance processing occurs and YCbCr samples are output during
the entire frame (default).
1 = Enabled. If bit 7, 2× luma output enable, is 0, normal luminance processing occurs and YCbCr samples are output during
VACTIVE and 2× luma samples are output during VBLK. Luminance bypass occurs for the duration of the vertical blanking
as defined by registers 18h and 19h.
Luma signal delay with respect to chroma signal in pixel clock increments (range –8 to 7 pixel clocks):
1111 = –8 pixel clocks delay
1011 = –4 pixel clocks delay
1000 = –1 pixel clocks delay
0000 = 0 pixel clocks delay (default)
0011 = 3 pixel clocks delay
0111 = 7 pixel clocks delay
7.2.9 Luminance Processing Control #2 Register
Address 08h
Default 00h
7 6 5 4 3 2 1 0
Reserved Luminance filter select Reserved Peaking gain Reserved
Luminance filter select:
0 = Luminance comb filter enabled (default)
1 = Luminance chroma trap filter enabled
Peaking gain (sharpness):
00 = 0 (default)
01 = 0.5
10 = 1
11 = 2
Information on peaking frequency: ITU-R BT.601 sampling rate: all standards — peaking center frequency is 2.6 MHz
34 Internal Control Registers Copyright © 2007–2010, Texas Instruments Incorporated
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