Datasheet

M
U
X
PALI
0
1
PALI/HLK/HVLK
HLK/HVLK
M
U
X
VSYNC
0
1
VSYNC/PALI/HLK/HVLK
0F(Bit 2)
VSYNC/PALI
M
U
X
VLK/HVLK 1
0
GLCO
FID
M
U
X
FID/VLK/HVLK
0
1
FID/GLCO/VLK/HVLK
0F(Bit 3)
FID/GLCO
03(Bit 4)
HVLK
M
U
X
HLK
0
1
HVLK
0F(Bit 4)
LOCK24B
M
U
X
HVLK
1
0
VLK
0F(Bit 6)
LOCK23
M
U
X
VBLK
1
0
INTREQ
GPCL
M
U
X
VBLK/GPCL
1
0
INTREQ/GPCL//VBLK
03(Bit 7)
VBKO
0F(Bit 1)
INTREQ/GPCL/VBLK
PCLK
M
U
X
CLK
0
1
PCLK/CLK
0F(Bit 0)
CLK/PCLK
Pins 38, 57, 76, 95
Pins 37, 56, 75, 94
Pins 41, 60, 83, 102
Pins 42, 61, 84, 103
TVP5154A
SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010 www.ti.com
NOTE: Also see the configuration shared pins register at subaddress 0Fh (Section 7.2.16).
Figure 7-1. Configuration Shared Pins
32 Internal Control Registers Copyright © 2007–2010, Texas Instruments Incorporated
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