Datasheet

TVP5154A
www.ti.com SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010
7.2.4 Miscellaneous Control Register
Address 03h
Default 01h
7 6 5 4 3 2 1 0
VBKO GPCL pin GPCL output Lock status YCbCr output HSYNC, VSYNC/PALI, Vertical blanking CLK output
enable (HVLK) enable(TVPOE) AVID, FID/GLCO output on/off enable
enable
VBKO (pins 41, 60, 83, 102) function select:
0 = GPCL (default)
1 = VBLK
Note, if these pins are not configured as outputs, they must not be left floating. A 10-kΩ pulldown resistor is recommended if
not driven externally.
GPCL (data is output based on state of bit 5):
0 = GPCL outputs 0 (default)
1 = GPCL outputs 1
GPCL output enable:
0 = GPCL is inactive (default). GPCL should not be programmed to 0 when register 0Fh bit 1 is 1 (programmed to be
GPCL/VBLK).
1 = GPCL is output.
Note that, if these pins are not configured as outputs, they must not be left floating. A 10-kΩ pulldown resistor is
recommended if not driven externally.
Lock status (HVLK) (configured along with register 0Fh, see Figure 7-1 for the relationship between the configuration shared pins):
0 = Terminal VSYNC/PALI outputs the PAL indicator (PALI) signal and terminal FID/GLCO outputs the field ID (FID) signal
(default) (if terminals are configured to output PALI and FID in register 0Fh).
1 = Terminal VSYNC/PALI outputs the horizontal lock indicator (HLK) and terminal FID outputs the vertical lock indicator (VLK) (if
terminals are configured to output PALI and FID in register 0Fh).
These are additional functionalities that are provided for ease of use.
YCbCr output enable:
0 = YOUT[7:0] high impedance (default)
1 = YOUT[7:0] active
Note, if these pins are not configured as outputs, they must not be left floating. A 10-kΩ pulldown resistor is recommended if
not driven externally.
HSYNC, VSYNC/PALI, active video indicator (AVID), and FID/GLCO output enables:
0 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high impedance (default).
1 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are active.
Note, if these pins are not configured as outputs, they must not be left floating. A 10-kΩ pulldown resistor is recommended if
not driven externally.
Vertical blanking on/off:
0 = Vertical blanking (VBLK) off (default)
1 = Vertical blanking (VBLK) on
CLK output enable:
0 = CLK output is high impedance.
1 = CLK output is enabled (default).
Note: CLK edge and SCLK are configured through register 05h.
Table 7-3. Digital Output Control
REGISTER 03h, REGISTER C2h,
YCbCr OUTPUT
BIT 3 (TVPOE)
(1)
BIT 2 (VDPOE)
(1)
0 X High impedance
X 0 High impedance
1 1 Active
(1) VDPOE default is 1 and TVPOE default is 0.
Copyright © 2007–2010, Texas Instruments Incorporated Internal Control Registers 31
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