Datasheet

TVP5154A
SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010 www.ti.com
Table 7-1. Direct Register Summary (continued)
REGISTER FUNCTION ADDRESS DEFAULT R/W
(1)
VDP configuration RAM data C3h B8h R/W
Configuration RAM address low byte C4h 1Fh R/W
Configuration RAM address high byte C5h 00h R/W
VDP status register C6h R
FIFO word count C7h R
FIFO interrupt threshold C8h 80h R/W
FIFO reset C9h 00h W
Line number interrupt CAh 00h R/W
Pixel alignment register low byte CBh 4Eh R/W
Pixel alignment register high byte CCh 00h R/W
FIFO output control CDh 01h R/W
Reserved CEh
Full field enable CFh 00h R/W
D0h 00h
Line mode registers R/W
D1h–FBh FFh
Full field mode register FCh 7Fh R/W
Reserved FDh
Decoder core write enables FEh 0Fh R/W
Decoder core read enables FFh 00h R/W
28 Internal Control Registers Copyright © 2007–2010, Texas Instruments Incorporated
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