Datasheet

CLK
GLCO
23-Bit Frequency Control
Start Bit DCO Reset Bit
MSB
>128 CLK
1 CLK
7 CLK23 CLK
1 CLK
LSB
22 21
0
RTC
M
S
B
16 CLK
L
S
B
21
0
128 CLK
22-Bit Fsc Frequency Control
Start
Bit
Reset
Bit
2 CLK
1 CLK
2 CLK
3 CLK
1 CLK
PAL
Switch
44 CLK
GLCO Timing
TVP5154A
SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010 www.ti.com
Figure 6-1. RTC Timing
6.3 Reset and Power Down
The RESETB and PDN terminals work together to put the TVP5154A decoder into one of the two modes.
Table 6-1 shows the configuration.
After power-up, the device is in an unknown state with its outputs undefined, until it receives a RESETB
signal as depicted in Figure 6-2. After RESETB is released, the data (CHn_OUT[7:0]), sync (HSYNCn,
VSYNCn/PALIn), and clock (CLKn, SCLKn) outputs are Hi-Z until the chip is initialized and the outputs are
activated.
NOTE
I2C SCL and SDA signals must not change state until the TVP5154A reset sequence has
been completed.
24 Genlock Control and RTC Copyright © 2007–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TVP5154A