Datasheet

F
dto
+
F
ctrl
2
23
F
clk
TVP5154A
www.ti.com SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010
6 Genlock Control and RTC
A Genlock control (GLCO) function is provided to support a standard video encoder to synchronize its
internal color oscillator for properly reproduced color with unstable timebase sources like VCRs.
The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the
subcarrier phase reset bit are transmitted via the GLCO terminal. The frequency control word is a 23-bit
binary number. The frequency of the DTO can be calculated from the following equation:
(1)
where F
dto
is the frequency of the DTO, F
ctrl
is the 23–bit DTO frequency control, and F
clk
is the frequency
of the CLK.
6.1 TVP5154A Genlock Control Interface
A write of 1 to bit 4 of the chrominance control register at I
2
C subaddress 1Ah causes the subcarrier DTO
phase reset bit to be sent on the next scan line on GLCO. The active-low reset bit occurs seven CLKs
after the transmission of the last bit of DCO frequency control. Upon the transmission of the reset bit, the
phase of the TVP5154A internal subcarrier DCO is reset to zero.
A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to
synchronize its internal color phase DCO to achieve clean line and color lock.
6.2 RTC Mode
Figure 6-1 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is four times slower
than the GLCO clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control
bit is two clock cycles long. The active-low reset bit occurs six CLKs after the transmission of the last bit of
PLL frequency control.
Copyright © 2007–2010, Texas Instruments Incorporated Genlock Control and RTC 23
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