Datasheet

124
XIN/OSC
14.31818-MHz
Crystal
C
L1
C
L2
XOUT
123
R
TVP5154A
124
XIN/OSC
XOUT
123
TVP5154A
14.31818-MHz
1.8-V Clock
NC
TVP5154A
SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010 www.ti.com
5 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to
drive the PLL. This may be input to the TVP5154A decoder on terminal 124 (XIN), or a crystal of
14.31818-MHz fundamental resonant frequency may be connected across terminals 123 and 124 (XIN
and XOUT). Figure 5-1 shows the reference clock configurations. For the example crystal circuit shown (a
parallel-resonant crystal with 14.31818-MHz fundamental frequency), the external capacitors must have
the following relationship:
C
L1
= C
L2
= 2C
L
– C
STRAY
where C
STRAY
is the terminal capacitance with respect to ground and C
L
is the crystal load capacitance
specified by the crystal manufacturer. Figure 5-1 shows the reference clock configurations.
NOTE: The resistor (R) in parallel with the crystal is recommended to support a wide range of crystal types. A 100-kΩ resistor
may be used for most crystal types.
Figure 5-1. Clock and Crystal Connectivity
22 Clock Circuits Copyright © 2007–2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TVP5154A