Datasheet
TVP5154A
www.ti.com
SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010
Read Phase 1
Step 1 0
I
2
C start (master) S
Step 2 7 6 5 4 3 2 1 0
I
2
C general address (master) 1 0 1 1 1 0 X 0
Step 3 9
I
2
C acknowledge (slave) A
Step 4 7 6 5 4 3 2 1 0
I
2
C read register address (master) addr addr addr addr addr addr addr addr
Step 5 9
I
2
C acknowledge (slave) A
Step 6 0
I
2
C stop (master) P
Read Phase 2
Step 7 0
I
2
C start (master) S
Step 8 7 6 5 4 3 2 1 0
I
2
C general address (master) 1 0 1 1 1 0 X 1
Step 9 9
I
2
C acknowledge (slave) A
Step 10 7 6 5 4 3 2 1 0
I
2
C read data (slave) Data Data Data Data Data Data Data Data
Step 11
(1)
9
I
2
C not acknowledge (master) A
Step 12 0
I
2
C stop (master) P
(1) Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
4.2.1 I
2
C Timing Requirements
The TVP5154A decoder requires delays in the I
2
C accesses to accommodate its internal processor's
timing. In accordance with I
2
C specifications, the TVP5154A decoder holds the I
2
C clock line (SCL) low to
indicate the wait period to the I
2
C master. If the I
2
C master is not designed to check for the I
2
C clock line
held-low condition, the maximum delays must always be inserted where required. These delays are of
variable length; maximum delays are indicated in the following diagram:
Table 4-3. I
2
C Timing
Slave address
Start Ack Subaddress Ack Data (XXh) Ack Wait 128 µs
(1)
Stop
(B8h)
(1) If the SCL pin is not monitored by the master to enable pausing, a delay of 128 µs should be inserted between transactions for registers
00h through 8Fh.
Copyright © 2007–2010, Texas Instruments Incorporated Clock Circuits 21
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