Datasheet

Decoder
Scaler
Delay
54MHz
/2 =
SCLK
CLK
Data
Mode
CLK edge
SCLK edge
00
01
Mode
=4
=1
=0
=2/3
!=3
=3
CLK OE
SCLK OE
Blank
=01
=11
=00
Decoder
Scaler
Delay
54 MHz
/2 =
27 MHz
SCLK
CLK
Data
Mode
CLK edge
SCLK edge
00
01
Mode
=4
=1
=0
=2/3
!=3
=3
CLK OE
SCLK OE
Blank
=01
=11
=00
Field mode(0)
Field mode(1)
Field mode(2)
Field mode(3)
Field mode(4)
Field mode(5)
Field mode(6)
Field mode(7)
Field mode(8)
Field mode(9)
Field mode(10)
Field mode(11)
Field mode(12)
Field mode(13)
Field mode(14)
Field mode(15)
TVP5154A
SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010 www.ti.com
3.15 Clock and Data Control
Figure 3-7 shows a logical schematic of the data and clock control signals.
Figure 3-7. Clock and Data Control
18 Functional Description Copyright © 2007–2010, Texas Instruments Incorporated
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