Datasheet

TVP5154A

www.ti.com

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

3.14 Embedded Syncs

Standards with embedded syncs insert SAV and EAV codes into the data stream at the beginning and end

of horizontal blanking. These codes contain the V and F bits that also define vertical timing. F and V

change on EAV. Table 3-4 gives the format of the SAV and EAV codes.

H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line

and field counter varies depending on the standard. See ITU-R BT.656 for more information on embedded

syncs.

The P bits are protection bits:

P3 = V x or

H P2 = F x or

H P1 = F x or

V P0 = F x or

V x or H

Table 3-4. EAV and SAV Sequence

8-BIT DATA

D7 (MSB) D6 D5 D4 D3 D2 D1 D0

Preamble 1 1 1 1 1 1 1 1

Preamble 0 0 0 0 0 0 0 0

Status word 1 F V H P3 P2 P1 P0

The status word may be modified to pass information about whether the current data corresponds to

scaled or unscaled data. See register 1Fh for more information.

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