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TVP5154A

www.ti.com

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

4-Channel Low-Power PAL/NTSC/SECAM Video Decoder

With Independent Scalers and Fast Lock

Check for Samples: TVP5154A

1 Introduction

1.1 Features

• Four Separate Video Decoder Channels With • Internal Phase-Locked Loop (PLL) for

Features for Each Channel: Line-Locked Clock (Separate for Each Channel)

and Sampling

– Accept NTSC (J, M, 4.43), PAL (B, D, G, H, I,

M, N, Nc), and SECAM (B, D, G, K, K1, L) • Sub-Carrier Genlock Output for Synchronizing

Video Color Sub-Carrier of External Encoder

– Support ITU-R BT.601 Standard Sampling • Standard Programmable Video Output Format

– High-Speed 9-Bit Analog-to-Digital Converter – ITU-R BT.656, 8-Bit 4:2:2 With Embedded

(ADC) Syncs

– Two Composite Inputs or One S-Video Input – 8-Bit 4:2:2 With Discrete Syncs

(for Each Channel)

• Advanced Programmable Video Output

– Fully Differential CMOS Analog Formats

Preprocessing Channels With Clamping and

– 2× Over-Sampled Raw Vertical Blanking

Automatic Gain Control (AGC) for Best

Interval (VBI) Data During Active Video

Signal to Noise (SNR) Performance

– Sliced VBI Data During Horizontal Blanking

– Brightness, Contrast, Saturation, Hue, and

or Active Video

Sharpness Control Through Inter-Integrated

• VBI Modes Supported:

Circuit (I

– Teletext (NABTS, WST)

– Complementary 4-Line (3-H Delay) Adaptive

– Closed-Caption Decode With FIFO, and

Comb Filters for Both Cross-Luminance and

Extended Data Services (EDS)

Cross-Chrominance Noise Reduction

– Wide Screen Signaling (WSS), Video

– Patented Architecture for Locking to Weak,

Program System (VPS), Copy Generation

Noisy, or Unstable Signals

Management System (CGMS), Vertical

• Four Independent Polymorphic Scalers

Interval Time Code (VITC)

• Single or Concurrent Scaled and Unscaled

– Gemstar 1×/2× Electronic Program Guide

Outputs Via Dual Clocking Data, Interleaved

Compatible Mode

54-MHz Data or Single 27-MHz Clock

– Custom Configuration Mode Allows User to

• Scaled/Unscaled Image Toggle Mode Gives

Program the Slice Engine for Unique VBI

Variable Field Rate for Both Scaled and

Data Signals

Unscaled Video

• Improved Fast Lock Mode Can Be Used When

• Low Power Consumption: 700 mW Typical

Input Video Standard Is Known and Signals on

• 128-Pin Thin Quad Flat Pack (TQFP) Package

Switching Channels Are Clean

• Single 14.31818-MHz Crystal for All Standards

• Four Possible I

C Addresses Allowing 16

and All Channels

Decoder Channels on a Single I

C Bus

• Available in Commercial (0°C to 70°C) and

Industrial (–40°C to 85°C) Temperature Ranges

1.2 Description

The TVP5154A device is a 4-channel, low-power, NTSC/PAL/SECAM video decoder. Available in a

space-saving 128-pin thin quad flat pack (TQFP) package, each channel of the TVP5154A decoder

converts NTSC, PAL, or SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (93 pages)

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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 4-Channel Low-Power PAL/NTSC/SECAM Video Decoder With Independent Scalers and Fast Lock Check for Samples: TVP5154A 1 Introduction 1.1 Features 1 • Four Separate Video Decoder Channels With Features for Each Channel: – Accept NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc), and SECAM (B, D, G, K, K1, L) Video – Support ITU-R BT.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com available. All four channels of the TVP5154A are independently controllable. The decoders share one crystal for all channels and for all supported standards. The TVP5154A can be programmed using a single inter-integrated circuit (I2C) serial interface. The decoder uses a 1.8-V supply for its analog and digital supplies, and a 3.3-V supply for its I/O. The optimized architecture of the TVP5154A decoder allows for low power consumption.
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TVP5154A www.ti.com 1.4 Related Products • • • • • 1.5 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 TVP5150AM1 TVP5151 TVP5146M2 TVP5147M1 TVP5158 Trademarks PowerPAD is a trademark of Texas Instruments. Macrovision is a trademark of Macrovision Corporation. Gemstar is a trademark of Gemstar-TV Guide International. Other trademarks are the property of their respective owners. 1.6 Document Conventions Throughout this data manual, several conventions are used to convey information.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 1 2 3 4 .............................................. 1 1.1 Features .............................................. 1 1.2 Description ........................................... 1 1.3 Applications .......................................... 2 1.4 Related Products ..................................... 3 1.5 Trademarks .......................................... 3 1.6 Document Conventions .............................. 3 1.7 Ordering Information .
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 2.2 www.ti.
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TVP5154A www.ti.com 2.3 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION I Analog inputs for Channel 1. Connect to the video analog input via a 0.1-µF capacitor. The maximum input range is 0–0.75 VPP, and may require an attenuator to reduce the input amplitude to the desired level. If not used, connect to AGND via a 0.1-µF capacitor. See the schematic in Section 10. I Analog inputs for Channel 2. Connect to the video analog input via a 0.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 TERMINAL NAME NO. I/O www.ti.com DESCRIPTION HSYNC1 HSYNC2 HSYNC3 HSYNC4 100 77 58 39 O Horizontal synchronization VSYNC1/PALI1 VSYNC2/PALI2 VSYNC3/PALI3 VSYNC4/PALI4 95 76 57 38 O 1. 2. PDN 122 I Power down (active low). A 0 on this pin puts the decoder in standby mode. PDN preserves the value of the registers. RESETB 121 I Active-low reset. RESETB can be used only when PDN = 1.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 3 Functional Description 3.1 Analog Front End Each channel of the TVP5154A decoder has an analog input channel that accepts two video inputs, which should be ac coupled through 0.1-µF capacitors. The decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is needed for standard input signals with a peak-to-peak variation of 1.5 V.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 3.3 www.ti.com Adaptive Comb Filtering The 4-line comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the luma path, then chroma trap filters are used which are shown in Figure 3-1 and Figure 3-2.
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TVP5154A www.ti.com 3.4 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Color Low-Pass Filter In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true in the case of video signals that have asymmetrical Cb/Cr sidebands. The provided color LP filters limit the bandwidth of the Cb/Cr signals. Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input image.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 3.8 www.ti.com VBI Data Processor The TVP5154A VBI data processor (VDP) slices various data services, such as teletext (WST, NABTS), closed caption (CC), wide screen signaling (WSS), etc. These services are acquired by programming the VDP to enable standards in the VBI. The results are stored in a FIFO and/or registers. The teletext results are stored in a FIFO only.
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TVP5154A www.ti.com 3.9 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 VBI FIFO and Ancillary Data in Video Stream Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is output during the horizontal blanking period following the line from which the data was retrieved. Table 3-2 shows the header format and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into the FIFO.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com 3.10 Raw Video Data Output The TVP5154A decoder can output raw A/D video data at 2× sampling rate for external VBI slicing. This is transmitted as an ancillary data block during the active horizontal portion of the line and during vertical blanking. 3.11 Output Formatter The output formatter is responsible for generating the output digital video stream. The YCbCr digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com Registers 13h and 14h provide access to stop pixels MSB and LSB, respectively. The vertical AVID cropping is controlled using the vertical blanking (VBLK) start and stop registers at addresses 18h and 19h. Figure 3-6 shows an AVID application. AVID cropping can be independently controlled for scaled (registers 25h, 26h, 29h, and 2Ah) and unscaled (registers 11h thru 14h) data streams.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 3.14 Embedded Syncs Standards with embedded syncs insert SAV and EAV codes into the data stream at the beginning and end of horizontal blanking. These codes contain the V and F bits that also define vertical timing. F and V change on EAV. Table 3-4 gives the format of the SAV and EAV codes. H equals 1 always indicates EAV. H equals 0 always indicates SAV.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com 3.15 Clock and Data Control Figure 3-7 shows a logical schematic of the data and clock control signals.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 4 I2C Host Interface The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. The input pins I2CA0 and I2CA1 are used to select the slave address to which the device responds. Although the I2C system can be multimastered, the TVP5154A decoder functions as a slave device only.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 4.1 www.ti.com I2C Write Operation Data transfers occur utilizing the following illustrated formats. An I2C master initiates a write operation to the TVP5154A decoder by generating a start condition (S) followed by the TVP5154A I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com 5 Clock Circuits An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL. This may be input to the TVP5154A decoder on terminal 124 (XIN), or a crystal of 14.31818-MHz fundamental resonant frequency may be connected across terminals 123 and 124 (XIN and XOUT). Figure 5-1 shows the reference clock configurations.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 6 Genlock Control and RTC A Genlock control (GLCO) function is provided to support a standard video encoder to synchronize its internal color oscillator for properly reproduced color with unstable timebase sources like VCRs. The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the subcarrier phase reset bit are transmitted via the GLCO terminal.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com CLK GLCO 22 MSB LSB 21 0 >128 CLK 23 CLK 23-Bit Frequency Control 7 CLK 1 CLK 1 CLK Start Bit DCO Reset Bit GLCO Timing L S B M S B RTC 0 21 128 CLK 16 CLK 44 CLK 1 CLK 22-Bit Fsc Frequency Control 2 CLK PAL Switch 2 CLK Start Bit 3 CLK 1 CLK Reset Bit Figure 6-1. RTC Timing 6.3 Reset and Power Down The RESETB and PDN terminals work together to put the TVP5154A decoder into one of the two modes.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Table 6-1. Reset and Power-Down Modes PDN RESETB 0 0 Reserved (unknown state) CONFIGURATION 0 1 Powers down the decoder 1 0 Resets the decoder 1 1 Normal operation PLL_AVDD DVDD IO_DVDD t1 Normal Operation RESETB Reset t2 PDN t3 SDA Data SCL Figure 6-2. Power-On Reset Timing Table 6-2. Power-On Reset Timing NO.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com 7 Internal Control Registers 7.1 Overview The TVP5154A decoder is initialized and controlled by sets of internal registers that set all device operating parameters. Communication between the external controller and the TVP5154A decoder is through the I2C. Two sets of registers exist, direct and indirect. Table 7-1 shows the summary of the direct registers. Reserved registers must not be written.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Table 7-1.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com Table 7-1.
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TVP5154A www.ti.com 7.2 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Direct Register Definitions Direct registers are written to by performing a 3-byte I2C transaction: START : DEVICE_ID : SUB_ADDRESS : DATA : STOP Each direct register is eight bits wide. 7.2.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.2 www.ti.com Analog Channel Controls Register Address Default 01h 15h 7 6 Reserved 5 4 1 3 0 2 1 1 0 Automatic gain control Automatic gain control (AGC): 00 = AGC disabled (fixed gain value) 01 = AGC enabled (default) 10 = Reserved 11 = AGC frozen to the previously set value 7.2.
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TVP5154A www.ti.com 7.2.4 Address Default 7 VBKO SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Miscellaneous Control Register 03h 01h 6 GPCL pin 5 GPCL output enable 4 Lock status (HVLK) 3 YCbCr output enable(TVPOE) 2 HSYNC, VSYNC/PALI, AVID, FID/GLCO output enable 1 Vertical blanking on/off 0 CLK output enable VBKO (pins 41, 60, 83, 102) function select: 0 = GPCL (default) 1 = VBLK Note, if these pins are not configured as outputs, they must not be left floating.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.
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TVP5154A www.ti.com 7.2.5 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Autoswitch Mask Register Address Default 04h DCh 7 6 Reserved N443_OFF: 0= 1= PALN_OFF: 0= 1= PALM_OFF: 0= 1= SEC_OFF: 0= 1= 7.2.6 5 SEC_OFF 4 N443_OFF 3 PALN_OFF 2 PALM_OFF 1 0 Reserved NTSC443 is unmasked from the autoswitch process. Autoswitch does switch to NTSC443. NTSC443 is masked from the autoswitch process. Autoswitch does not switch to NTSC443 (default). PAL-N is unmasked from the autoswitch process.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.8 www.ti.com Luminance Processing Control #1 Register Address Default 07h 60h 7 2× luma output enable 6 Pedestal not present 5 Disable raw header 4 Luma bypass enabled during vertical blanking 3 2 1 0 Luminance signal delay with respect to chrominance signal 2× luma output enable: 0 = Output depends on bit 4, luminance bypass enabled during vertical blanking (default). 1 = Outputs 2x luma samples during the entire frame.
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TVP5154A www.ti.com 7.2.10 Address Default SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Brightness Control Register 09h 80h 7 6 5 4 3 Brightness control 2 1 0 Brightness control: This register works for CVBS and S-Video luminance. 1111 1111 = 255 (bright) 1000 0000 = 128 (default) 0000 0000 = 0 (dark) The output black level relative to the nominal black level (16 out of 256) as a function of the Brightness[7:0] setting and the Contrast[7:0] setting is as follows.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com 7.2.13 Contrast Control Register Address Default 0Ch 80h 7 6 5 4 3 2 1 0 Contrast [7:0] Contrast [7:0]: This register works for CVBS and S-Video luminance. 1111 1111 to 1101 Reserved 0000 = 1100 1111 = 207 (maximum contrast) 1000 0000 = 128 (default) 0000 0000 = 0 (minimum contrast) The total luminance gain relative to the nominal luminance gain as a function of the Contrast [7:0] setting is as follows.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.15 Luminance Processing Control #3 Register Address Default 7 0Eh 00h 6 5 4 3 2 Reserved 1 0 Luminance trap filter select Luminance filter stop band bandwidth (MHz): 00 = No notch (default) 01 = Notch 1 10 = Notch 2 11 = Notch Luminance filter select [1:0] selects one of the four chroma trap (notch) filters to produce luminance signal by removing the chrominance signal from the composite video signal.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.16 Address Default 7 Reserved www.ti.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.21 www.ti.com Genlock and RTC Register Address Default 15h 01h 7 Stable syncs 6 Reserved 5 4 3 Auto inc F/V bit control 2 1 GLCO/RTC 0 Stable syncs 0 = Output F and V bits follow the input signal producing fixed vertical blanking periods by adapting the active video. 1 = Output F and V bits produce fixed active video periods by adapting the vertical blanking. F/V bit control Table 7-5.
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TVP5154A www.ti.com 7.2.22 Address Default SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Horizontal Sync (HSYNC) Start Register 16h 80h 7 6 5 4 3 2 1 0 HSYNC start HSYNC start: 1111 1111 = 1111 1110 = 1000 0001 = 1000 0000 = 0111 1111 = 0111 1110 = 0000 0000 = –127 × 4 pixel clocks –126 × 4 pixel clocks –1 × 4 pixel clocks 0 pixel clocks (default) 1 × 4 pixel clocks 2 × 4 pixel clocks 128 × 4 pixel clocks BT.656 SAV Code BT.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.23 www.ti.com Ancillary SAV/EAV Control Address Default 7 Reserved 17h 52h 6 Scaler PD 5 Include scale ancillary 4 Include scale SAV 3 Include scale EAV 2 Include unscale ancillary 1 Include unscale SAV 0 Include unscale EAV Include unscaled EAV: 0 = AVID period does not include the EAV sync codes (default). 1 = AVID period includes the EAV sync codes. Include unscaled SAV: 0 = AVID period does not include the SAV sync codes.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Data www.ti.
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TVP5154A www.ti.com 7.2.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.26 www.ti.com Chrominance Control #1 Register Address Default 1Ah 0Ch 7 6 5 Reserved color 4 PLL reset 3 Chrominance adaptive comb filter enable (ACE) 2 Chrominance comb filter enable (CE) 1 0 Automatic color gain control Color PLL reset: 0 = Color PLL not reset (default) 1 = Color PLL reset Writing a 1 to this bit resets the color PLL and transmits a 1 in the reset bit of the GLCO output stream.
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TVP5154A www.ti.com 7.2.28 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Interrupt Reset Register B Address Default 7 Software initialization reset 1Ch 00h 6 Reserved 5 Reserved 4 Field rate changed reset 3 Line alternation changed reset 2 Color lock changed reset 1 H/V lock changed reset 0 TV/VCR changed reset Interrupt reset register B is used by the external processor to reset the interrupt status bits in interrupt status register B.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.29 Address Default www.ti.
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TVP5154A www.ti.com 7.2.30 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Interrupt Configuration Register B Address Default 1Eh 00h 7 6 5 4 Reserved 3 2 1 0 Interrupt polarity B Interrupt polarity B: 0 = Interrupt B is active low (default). 1 = Interrupt B is active high. Interrupt polarity B must be same as interrupt polarity A bit at bit 0 of the interrupt configuration register A at address C2h.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com 7.2.33 Indirect Register Read/Write Strobe Address Default 7 24h 00h 6 5 4 3 2 1 0 R/W[7:0] This register selects the most significant bits of the indirect register address and performs either an indirect read or write operation. Data will be written from are read to Indirect Register Data registers 21h-22h.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.35 Address Default www.ti.com Active Video Cropping Start Pixel MSB for Scaled Data Register 25h 00h 7 6 5 4 3 AVID start pixel MSB [9:2] 2 1 0 Active video cropping start pixel MSB [9:2], set this register first before setting register 26h. The TVP5154A decoder updates the AVID start values only when register 26h is written to. This start pixel value is relative to the default values of the AVID start pixel. 7.2.
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TVP5154A www.ti.com 7.2.37 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Video Standard Register Address Default 28h 00h 7 6 5 4 3 2 Reserved Video standard: 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1 0 Video standard Autoswitch mode (default) Reserved (M, J) NTSC ITU-R BT.601 Reserved (B, G, H, I, N) PAL ITU-R BT.601 Reserved (M) PAL ITU-R BT.601 Reserved (Combination-N) PAL ITU-R BT.601 Reserved NTSC 4.43 ITU-R BT.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.40 Address www.ti.com Cb Gain Factor Register 2Ch 7 6 5 4 3 2 1 0 Cb gain factor This is a read-only register that provides the gain applied to the Cb in the YCbCr data stream. 7.2.41 Address Cr Gain Factor Register 2Dh 7 6 5 4 3 2 1 0 Cr gain factor This is a read-only register that provides the gain applied to the Cr in the YCbCr data stream. 7.2.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.45 Patch Code Execute Address Default 7Fh 00h 7 6 5 4 3 2 1 0 R/W[7:0] Writing to this register following a firmware patch load restarts the CPU and initiates execution of the patch code. This register must not be written to or read from during normal operation. 7.2.46 LSB of Device ID Register Address Default 81h 54h 7 6 5 4 3 LSB of device ID 2 1 0 2 1 0 This register identifies the LSB of the device ID.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.48 Address Default ROM Minor Version Register 83h 00h 7 (1) www.ti.com 6 5 4 3 ROM minor version (1) 2 1 0 This register can contain a number from 0x01 to 0xFF. 7.2.49 Address Vertical Line Count MSB Register 84h 7 6 5 4 3 2 Reserved 1 0 Vertical line count MSB Vertical line count bits [9:8] 7.2.
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TVP5154A www.ti.com 7.2.51 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Interrupt Status Register B Address 7 Software initialization 86h 6 Reserved 5 Command ready 4 Field rate changed 3 Line alternation changed 2 Color lock changed 1 H/V lock changed 0 TV/VCR changed Software initialization: 0 = Software initialization is not ready (default). 1 = Software initialization is ready. Command ready: 0 = TVP5154A is not ready to accept a new command (default).
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.52 www.ti.com Interrupt Active Register B Address 87h 7 6 5 4 Reserved 3 2 1 0 Interrupt B Interrupt B: 0 = Interrupt B is not active on the external terminal (default). 1 = Interrupt B is active on the external terminal. The interrupt active register B is polled by the external processor to determine if interrupt B is active. 7.2.
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TVP5154A www.ti.com 7.2.54 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Status Register #2 Address 7 Reserved 89h 6 Weak signal detection 5 PAL switch polarity 4 Field sequence status 3 AGC and offset frozen status 2 1 0 Reserved Weak signal detection: 0 = No weak signal 1 = Weak signal mode PAL switch polarity of first line of odd field: 0 = PAL switch is 0. 1 = PAL switch is 1.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com 7.2.56 Status Register #4 Address 8Bh 7 6 5 4 3 Subcarrier to horizontal (SCH) phase 2 1 0 SCH (color PLL subcarrier phase at 50% of the falling edge of horizontal sync of line one of odd field; step size 360°/256): 0000 0000 = 0.00o 0000 0001 = 1.41o 0000 0010 = 2.81o 1111 1110 = 357.2o 1111 1111 = 358.6o 7.2.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.58 Patch Read Address Address Default 8Eh 00h 7 6 5 4 3 2 1 0 R/W[7:0] This register can be used for patch code read-back. This register must not be written to or read from during normal operation. 7.2.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com 7.2.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.68 Interrupt Configuration Register A Address Default 7 C2h 04h 6 5 Reserved 4 3 2 YCbCr enable (VDPOE) 1 Interrupt A 0 Interrupt polarity A YCbCr enable (VDPOE): 0 = YCbCr pins are high impedance. 1 = YCbCr pins are active if other conditions are met (default). Interrupt A (read only): 0 = Interrupt A is not active on the external pin (default). 1 = Interrupt A is active on the external pin.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com Table 7-11.
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TVP5154A www.ti.com 7.2.70 Address 7 FIFO full error SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 VDP Status Register C6h 6 FIFO empty 5 TTX available 4 CC field 1 available 3 CC field 2 available 2 WSS/CGMS-A available 1 VPS/Gemstar 2x available 0 VITC available The VDP status register indicates whether data is available in either the FIFO or data registers, and status information about the FIFO. Reading data from the corresponding register does not clear the status flags automatically.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.72 www.ti.com FIFO Interrupt Threshold Register Address Default C8h 80h 7 6 5 4 3 Number of words 2 1 0 This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value (default 80h). This interrupt must be enabled at address C1h. One word equals two bytes. 7.2.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.76 FIFO Output Control Register Address Default 7 CDh 01h 6 5 4 Reserved 3 2 1 0 Host access enable This register is programmed to allow I2C access to the FIFO or allowing all VDP data to go out the video port. Host access enable: 0 = Output FIFO data to the video output Y[7:0] 1 = Allow I2C access to the FIFO data (default) 7.2.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.2.78 Line Mode Registers Address Default Address D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh 72 www.ti.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 These registers program the specific VBI standard at a specific line in the video field. Bit 7: 0 = Disable filtering of null bytes in closed caption modes. 1 = Enable filtering of null bytes in closed caption modes (default). In teletext modes, bit 7 enables the data filter function for that particular line. If it is set to 0, the data filter passes all data on that line. Bit 6: 0 = Send VBI data to registers only.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com 7.2.79 Full Field Mode Register Address Default 7 FCh 7Fh 6 5 4 3 Full field mode 2 1 0 This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual line settings take priority over the full field register. This allows each VBI line to be programmed independently but have the remaining lines in full field mode.
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TVP5154A www.ti.com 7.3 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Indirect Register Definitions To write to the TVP5154A indirect registers, it is required that the registers be unlocked using a password. The password prevents undesirable writes into the device at start-up due to power surges, for example. The following example demonstrates the method for unlocking the indirect registers.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.3.1 www.ti.com DID Control Address Default 7 15 36Ah 000h 6 Unscaled field 1 DID 5 4 3 2 1 Unscaled field 0 DID 0 14 13 Scaled field 1 DID 12 11 10 9 Scaled field 0 DID 8 This register controls the value of the EAV DID bytes for scaled and unscaled data. The value for each field can be independently set, allowing identification of both which field is being processed and whether the data comes from the scaled or unscaled channel.
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TVP5154A www.ti.com 7.3.4 SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 Interleave Field Control 2 Address Default 36Eh 0h 7 6 5 Field mode(3) 15 14 13 Field mode(7) 7.3.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 7.3.7 www.ti.com Vertical Scaling Field 2 Control Address Default 3A9h 0h 7 6 5 4 3 2 1 0 11 10 9 8 V_Field2[8] 0 V_Field2[7:0] 15 14 13 12 Reserved Vertical scaling initial value in field 2 [8:0]: Initial value of vertical accumulator for field 2 For NTSC: V_Field2 = (Vdesired/Vactive) × 256 For PAL: V_Field2 = (1.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 8 Scaler Configuration 8.1 Overview The TVP5154A contains four independent scalers, one for each video decoder channel. Each scaler is able to filter and scale both horizontally and vertically to different ratios. Horizontally, a 7-tap poly-phase filter is used to ensure optimal scaling performance and can be configured to scale to any output size below the input resolution, in decrements of two pixels.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 8.3 8.3.1 www.ti.com Vertical Scaling Registers The vertical scaler implements a weighted running average filter, which requires the initial weights and the ratio registers to be configured. Additionally, it is necessary to program the input and output scaling control registers (3A8, 3A9, and 3AC). Figure 8-2 shows the active and inactive data lines when scaled vertically.
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TVP5154A www.ti.com 8.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 www.ti.com 9 Electrical Specifications Absolute Maximum Ratings (1) 9.1 over operating free-air temperature range (unless otherwise noted) VALUE Supply voltage range IOVDD to DGND –0.5 to 3.6 DVDD to DGND –0.5 to 2 PLL_AVDD to PLL_AGND –0.5 to 2 AVDD to AGND –0.5 to 2 –0.5 to 3.6 V Input voltage range, XIN to PLL_GND –0.5 to 2 V –0.2 to 2 V –0.5 to 3.
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TVP5154A www.ti.com 9.
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TVP5154A SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 9.5 www.ti.com Timing Requirements TEST CONDITIONS (1) PARAMETER MIN Duty cycle SCL TYP MAX 50 UNIT % t1 CLK high time (at 27 MHz) 13.5 t2 CLK low time (at 27 MHz) 13.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 t13 t14 CLK t15 Y/C & Syncs t16 Scaled Data 1 Unscaled Data 1 Unscaled Data 2 Scaled Data 2 t10 t11 t12 t12 Figure 9-3. Output Mode 3: Clock, Video Data, and Sync (Positive Edge Clock) I2C Host Port Timing 9.6 PARAMETER TEST CONDITIONS MIN MAX UNIT t1 Bus free time, between STOP and START 1.3 µs t2 Setup time, (repeated) START condition 0.6 µs t3 Hold time, (repeated) START condition 0.
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A B C 0.1uF C 0.1uF 1 37.4 R 37.4 R 37.4 R 37.4 R R 37.4 R 37.4 R 37.4 R 37.4 CH4_A CH3_A CH2_A CH1_A CH4_B IN CH3_B IN CH2_B IN CH1_B IN C 0.1uF C 0.1uF I2CA0 R 10k 2 R 10k IOVDD I2CA1 R 10k 2 R 10k IOVDD 2-3 Base Addr 0xB8 - Default I2C ADDRESS SELECTION CH4_A IN CH3_A IN CH2_A IN CH1_A IN REMEMBER 75ohm TERMINATION FOR 0-0.75V INPUT RANGE 1 3 C C 0.1uF INPUT V DIVIDER NETWORK C 0.1uF C 0.1uF DVDD 1 3 D C 0.1uF PLL_VDD 37.4 R 37.4 R 37.4 R 37.
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TVP5154A www.ti.com SLES214C – DECEMBER 2007 – REVISED SEPTEMBER 2010 11 Revision History Table 11-1. Revision History REVISION COMMENTS SLES214 Initial release SLES214A Industrial temperature devices added SLES214B Section 1.1, NTSC-J and PAL-Nc support added to feature list. Section 1.2, Application list modified. Section 1.4, Related Products modified. Section 1.5, Trademarks added. Section 1.6, Document conventions added. Section 2, Figure 2-1, Block diagram modified. Section 3.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-May-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.