Datasheet

TVP5151

www.ti.com

SLES241E–SEPTEMBER 2009– REVISED OCTOBER 2011

5 Example Register Settings

The following example register settings are provided only as a reference. These settings, given the

assumed input connector, video format, and output format, set up the TVP5151 decoder and provide

video output. Example register settings for other features and the VBI data processor are not provided

here.

5.1 Example 1

5.1.1 Assumptions

Device: TVP5151

Input connector: Composite (AIP1A)

Video format: NTSC-M, PAL (B, G, H, I), or SECAM

NOTE

NTSC-4.43, PAL-N, and PAL-M are masked from the autoswitch process by default. See the

autoswitch mask register at address 04h.

Output format: 8-bit ITU-R BT.656 with embedded syncs

5.1.2 Recommended Settings

Recommended I

C writes: For this setup, only one write is required. All other registers are set up by

default.

C register address 03h = Miscellaneous controls register address

C data 09h = Enables YCbCr output and the clock output

NOTE

HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high impedance by default. See the

miscellaneous control register at address 03h.

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