Datasheet

M
U
X
AIP1A
AIP1B
PGA
A/D
Output
Formatter
YOUT[7:0]
YCbCr 8-Bit
4:2:2
VBI Data
Processor (VDP)
Embedded Processor
XTAL1/OSC
XTAL2
SCLK
Horizontal and
Color PLLs
FID/GLCO
VSYNC/PALI
INTREQ/GPCL/VBLK
HSYNC
Timing Processor
SCL
SDA
Y/C Separation
Chrominance
Processing
Luminance
Processing
Macrovision
Detection
Host
Interface
AVID/CLK_IN
PDN
TVP5151
www.ti.com SLES241E–SEPTEMBER 2009– REVISED OCTOBER 2011
2 Device Details
2.1 Functional Block Diagram
Figure 2-1. Functional Block Diagram
Copyright © 2009–2011, Texas Instruments Incorporated Device Details 5
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