Datasheet

TVP5151

SLES241E–SEPTEMBER 2009–REVISED OCTOBER 2011

www.ti.com

3.21.20 Genlock and RTC Register

Address 15h

Default 01h

7 6 5 4 3 2 1 0

Reserved F/V bit control Reserved GLCO/RTC

F/V bit control

BIT 5 BIT 4 NUMBER OF LINES F BIT V BIT

Standard ITU-R BT.656 ITU-R BT.656

0 0 Nonstandard even Force to 1 Switch at field boundary

Nonstandard odd Toggles Switch at field boundary

Standard ITU-R BT.656 ITU-R BT.656

0 1

Nonstandard Toggles Switch at field boundary

Standard ITU-R BT.656 ITU-R BT.656

1 0

Nonstandard Pulse mode Switch at field boundary

1 1 Illegal

GLCO/RTC. The following table shows the different modes.

BIT 2 BIT 1 BIT 0 GENLOCK/RTC MODE

0 X 0 GLCO

RTC output mode 0

0 X 1

(default)

1 X 0 GLCO

1 X 1 RTC output mode 1

All other values are reserved.

Figure 3-9 shows the timing of GLCO, and Figure 3-10 shows the timing of RTC.

3.21.21 Horizontal Sync Start Register

Address 16h

Default 80h

7 6 5 4 3 2 1 0

HSYNC start

Horizontal sync (HSYNC) start

1111 1111 = –127 × 4 pixel clocks

1111 1110 = –126 × 4 pixel clocks

1000 0001 = –1 × 4 pixel clocks

1000 0000 = 0 pixel clocks (default)

0111 1111 = 1 × 4 pixel clocks

0111 1110 = 2 × 4 pixel clocks

0000 0000 = 128 × 4 pixel clocks

Submit Documentation Feedback