Datasheet

TVP5151

SLES241E–SEPTEMBER 2009–REVISED OCTOBER 2011

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3.21.15 Configuration Shared Pins Register

Address 0Fh

Default 00h

7 6 5 4 3 2 1 0

Reserved LOCK23 Reserved LOCK24B FID/GLCO VSYNC/PALI INTREQ/ Reserved, must

GPCL/VBLK be set to 0

LOCK23 (pin 23) function select

0 = FID (default, if bit 3 is selected to output FID)

1 = Lock indicator (indicates whether the device is locked vertically)

LOCK24B (pin 24) function select

0 = PALI (default, if bit 2 is selected to output PALI)

1 = Lock indicator (indicates whether the device is locked horizontally)

FID/GLCO (pin 23) function select (also see register 03h for enhanced functionality)

0 = FID (default)

1 = GLCO

VSYNC/PALI (pin 24) function select (also see register 03h for enhanced functionality)

0 = VSYNC (default)

1 = PALI

INTREQ/GPCL/VBLK (pin 27) function select

0 = INTREQ (default)

1 = GPCL or VBLK depending on bit 7 of register 03h

See Figure 3-12 for the relationship between the configuration shared pins.

3.21.16 Active Video Cropping Start Pixel MSB Register

Address 11h

Default 00h

7 6 5 4 3 2 1 0

AVID start pixel MSB [9:2]

Active video cropping start pixel MSB [9:2], set this register first before setting register 12h. The TVP5151

decoder updates the AVID start values only when register 12h is written to. This start pixel value is relative

to the default values of the AVID start pixel.

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