Datasheet

Pin 24
M
U
X
PALI 0
1
PALI/HLK/HVLK
HLK/HVLK
M
U
X
VSYNC 0
1
VSYNC/PALI/HLK/HVLK
0F(Bit 2)
VSYNC/PALI
Pin 23
M
U
X
VLK/HVLK 1
0
GLCO
FID
M
U
X
FID/VLK/HVLK 0
1
FID/GLCO/VLK/HVLK
0F(Bit 3)
FID/GLCO
03(Bit 4)
HVLK
M
U
X
HLK 0
1HVLK
0F(Bit 4)
LOCK24B
M
U
X
HVLK 1
0VLK
0F(Bit 6)
LOCK23
Pin 27
M
U
X
VBLK 1
0
INTREQ
GPCL
M
U
X
VBLK/GPCL 1
0
INTREQ/GPCL/VBLK
03(Bit 7)
VBKO 0F(Bit 1)
INTREQ/GPCL/VBLK
03(Bit 5)
GPCL Ouput Enable
TVP5151
www.ti.com SLES241E–SEPTEMBER 2009– REVISED OCTOBER 2011
Figure 3-12. Configuration Shared Pins
NOTE
Also see the configuration shared pins register at subaddress 0Fh.
Copyright © 2009–2011, Texas Instruments Incorporated Functional Description 33
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