Datasheet

RESETB
Normal Operation
Reset
PLL_AVDD
DVDD
IO_DVDD
SDA
PDN
SCL
Data
t1
t2
t3
TVP5151
SLES241E–SEPTEMBER 2009–REVISED OCTOBER 2011 www.ti.com
After RESETB is released, outputs SCLK and YOUT0 to YOUT7 are high-impedance until the chip is
initialized and the outputs are activated.
Figure 3-11. Power-On Reset Timing
Table 3-9. Power-On Reset Timing
NO. PARAMETER MIN MAX UNIT
t1 Delay time between power supplies active and reset 20 ms
t2 RESETB pulse duration 500 ns
t3 Delay time between end of reset to I
2
C active 200 µs
24 Functional Description Copyright © 2009–2011, Texas Instruments Incorporated
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