Datasheet
TVP5151
www.ti.com
SLES241E–SEPTEMBER 2009– REVISED OCTOBER 2011
3.15.1 I
2
C Write Operation
Data transfers occur utilizing the following illustrated formats.
An I
2
C master initiates a write operation to the TVP5151 decoder by generating a start condition (S)
followed by the TVP5151 I
2
C slave address (see the following illustration), in MSB first bit order, followed
by a 0 to indicate a write cycle. After receiving an acknowledge from the TVP5151 decoder, the master
presents the subaddress of the register, or the first of a block of registers it wants to write, followed by one
or more bytes of data, MSB first. The TVP5151 decoder acknowledges each byte after completion of each
transfer. The I
2
C master terminates the write operation by generating a stop condition (P).
Step 1 0
I
2
C Start (master) S
Step 2 7 6 5 4 3 2 1 0
I
2
C slave address (master) 1 0 1 1 1 0 X 0
Step 3 9
I
2
C Acknowledge (slave) A
Step 4 7 6 5 4 3 2 1 0
I
2
C Write register address (master) Addr Addr Addr Addr Addr Addr Addr Addr
Step 5 9
I
2
C Acknowledge (slave) A
Step 6 7 6 5 4 3 2 1 0
I
2
C Write data (master) Data Data Data Data Data Data Data Data
9
Step 7
(1)
I
2
C Acknowledge (slave) A
Step 8 0
I
2
C Stop (master) P
(1) Repeat steps 6 and 7 until all data have been written.
3.15.2 I
2
C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I
2
C
master initiates a write operation to the TVP5151 decoder by generating a start condition (S) followed by
the TVP5151 I
2
C slave address, in MSB first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the TVP5151 decoder, the master presents the subaddress of the register
or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates
the cycle immediately by generating a stop condition (P).
Table 3-7. Read Address
Selection
I2CSEL READ ADDRESS
0 B9h
1 BBh
The second phase is the data phase. In this phase, an I
2
C master initiates a read operation to the
TVP5151 decoder by generating a start condition followed by the TVP5151 I
2
C slave address (see the
following illustration of a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle.
After an acknowledge from the TVP5151 decoder, the I
2
C master receives one or more bytes of data from
the TVP5151 decoder. The I
2
C master acknowledges the transfer at the end of each byte. After the last
data byte desired has been transferred from the TVP5151 decoder to the master, the master generates a
not acknowledge followed by a stop.
Copyright © 2009–2011, Texas Instruments Incorporated Functional Description 19
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