Datasheet

Electrical Characteristics
57
May 2006 SLES043A
4.3.3 Timing
4.3.3.1 Clocks, Video Data, Sync Timing
PARAMETER
TEST CONDITIONS
(see NOTE 2)
MIN TYP MAX UNIT
Duty cycle PCLK, SCLK 50%
t
1
Delay time, SCLK falling edge to digital outputs
See Note 3 (by de-
sign)
2.8 8 ns
NOTES: 3. C
L
= 15 pF
4. All outputs are 3.3 V.
SCLK
HSYNC/VSYNC/AVID/
PALI/FID/Y[7:0]
t
1
Figure 4−1. Clocks, Video Data, and Sync Timing
4.3.3.2 I
2
C Host Port Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
Bus free time between STOP and START 1.3 µs
t
2
Setup time for a (repeated) START condition 0.6 µs
t
3
Hold time (repeated) START condition 0.6 µs
t
4
Setup time for a STOP condition 0.6 ns
t
5
Data setup time 100 ns
t
6
Data hold time 0 0.9 µs
t
7
Rise time VC1(SDA) and VC0(SCL) signal 250 ns
t
8
Fall time VC1(SDA) and VC0(SCL) signal 250 ns
C
b
Capacitive load for each bus line 400 pF
f
I2C
I
2
C clock frequency 400 kHz
t
5
Stop
Start
VC1 (SDA)
t
1
t
6
t
7
t
2
t
8
t
3
t
4
t
6
VC0 (SCL)
Data
Stop
Figure 4−2. I
2
C Host Port Timing