Datasheet

Functional Description
52
May 2006SLES043A
3.22.61 FIFO Output Control Register
Address CDh
7 6 5 4 3 2 1 0
Reserved Host access enable
This register is programmed to allow I
2
C access to the FIFO or allowing all VDP data to go out the video port.
Host access enable:
0 = Output FIFO data to the video output Y[9:2] (default)
1 = Allow I
2
C access to the FIFO data
3.22.62 Automatic Initialization Register
Address CEh
7 6 5 4 3 2 1 0
Reserved Auto initialize Auto clock Reserved
This register enables the VDP to preprogram the line mode registers for the most common standards based
on the video standard, that is, PAL, NTSC.
Auto initialize:
0 = Disable initialization of teletext and closed caption standards (default)
1 = Enable initialization of teletext and closed caption standards
Auto clock:
0 = Do not update bit 0 (default)
1 = Enable VDP to update bit 0
3.22.63 Full Field Enable Register
Address CFh
7 6 5 4 3 2 1 0
Reserved Full field enable
This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in
the line mode registers programmed with FFh are sliced with the definition of register FCh. Values other than
FFh in the line mode registers allow a different slice mode for that particular line.
Full field enable:
0 = Disable full field mode (default)
1 = Enable full field mode