Datasheet

Functional Description
47
May 2006 SLES043A
FIFO threshold interrupt:
0 = The amount of data in the FIFO has not yet crossed the threshold programmed at address C8h.
1 = The amount of data in the FIFO has crossed the threshold programmed at address C8h.
Line interrupt:
0 = The video line number has not yet been reached.
1 = The video line number programmed in address CAh has occurred.
Data interrupt:
0 = No data is available.
1 = VBI data is available either in the FIFO or in the VBI data registers.
3.22.52 Interrupt Enable Register A
Address C1h
7 6 5 4 3 2 1 0
Reserved
Lock interrupt
enable
Cycle complete
interrupt enable
Bus error
interrupt enable
Reserved
FIFO threshold
interrupt enable
Line interrupt
enable
Data interrupt
enable
The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits
loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin.
Conversely, bits loaded with a 0 mask the corresponding interrupt condition from generating an interrupt on
the external pin. This register only affects the interrupt on the external terminal, it does not affect the bits in
interrupt status register A. A given condition can set the appropriate bit in the status register and not cause
an interrupt on the external terminal. To determine if this device is driving the interrupt terminal either perform
a logical AND of interrupt status register A with interrupt enable register A, or check the state of the interrupt
A bit in the interrupt configuration register at address C2h.
Lock interrupt enable:
0 = Disabled (default)
1 = Enabled
Cycle complete interrupt enable:
0 = Disabled (default)
1 = Enabled
Bus error interrupt enable:
0 = Disabled (default)
1 = Enabled
FIFO threshold interrupt enable:
0 = Disabled (default)
1 = Enabled
Line interrupt enable:
0 = Disabled (default)
1 = Enabled
Data interrupt enable:
0 = Disabled (default)
1 = Enabled