Datasheet

Functional Description
46
May 2006SLES043A
3.22.50 Teletext Filter Control Register
Address BBh
7 6 5 4 3 2 1 0
Reserved Filter logic Mode TTX filter 2 enable TTX filter 1 enable
Filter logic: allows different logic to be applied when combining the decision of filter 1 and filter 2 as follows:
00 = NOR (Default)
01 = NAND
10 = OR
11 = AND
Mode:
0 = Teletext WST PAL mode B (2 header bytes) (default)
1 = Teletext NABTS NTSC mode C (5 header bytes)
TTX filter 2 enable:
0 = Disabled (default)
1 = Enabled
TTX filter 1 enable:
0 = Disabled (default)
1 = Enabled
If the filter matches or if the filter mask is all 0s, then a true result is returned.
3.22.51 Interrupt Status Register A
Address C0h
7 6 5 4 3 2 1 0
Lock state
interrupt
Lock interrupt
Cycle complete
interrupt
Bus error
interrupt
Reserved
FIFO threshold
interrupt
Line interrupt Data interrupt
The interrupt status register A can be polled by the host processor to determine the source of an interrupt. After
an interrupt condition is set it can be reset by writing to this register with a 1 in the appropriate bit(s).
Lock state interrupt:
0 = TVP5150 is not locked to the video signal.
1 = TVP5150 is locked to the video signal.
Lock interrupt:
0 = A transition has not occurred on the lock signal.
1 = A transition has occurred on the lock signal.
Cycle complete interrupt:
0 = Read or write cycle in progress
1 = Read or write cycle complete
Bus error interrupt:
0 = No bus error
1 = PHI interface detected an illegal access