Datasheet

Functional Description
33
May 2006 SLES043A
3.22.21 Genlock and RTC Register
Address 15h
7 6 5 4 3 2 1 0
Reserved CDTO_SW Reserved GLCO/ RTC
CDTO_LSB_Switch (CDTO_SW):
0 = CDTO_LSB is forced to 0
1 = CDTO_LSB is forced to 1 (default)
GLCO/RTC:
0 = GLCO output
1 = RTC output (default)
Figure 3−13 shows the timing of GLCO and Figure 3−14 shows the timing of RTC.
3.22.22 Horizontal Sync (HSYNC) Start Register
Address 16h
7 6 5 4 3 2 1 0
HSYNC start
HSYNC start:
1111 1111 = −127 x 4 pixel clocks
1111 1110 = −126 x 4 pixel clocks
1111 1101 = −125 x 4 pixel clocks
1000 0000 = 0 pixel clocks (default)
0111 1111 = 1 x 4 pixel clocks
0111 1110 = 2 x 4 pixel clocks
0000 0000 = 128 x 4 pixel clocks
U
BT.656 EAV Code
YOUT
[7:0]
H
SYNC
Y V Y 0
F
F
0
0
0
0
0
0
X
Y
Z
0
8
0
0
1
0
0
8
0
0
1
0
0
F
F
0
0
0
0
0
0
X
Y
Z
U
Y
AVID
128 SCLK
N
hbhs
N
hb
Start of
Digital Line
Start of Digital
Active Line
BT.656 SAV Code
Figure 3−15. Horizontal Sync
Table 3−11. Clock Delays (SCLKs)
STANDARD N
hbhs
N
hb
NTSC 601 32 272
PAL 601 24 284