Datasheet

Functional Description
23
May 2006 SLES043A
3.20.2 RTC Mode
Figure 3−14 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is 4 times slower than
the GLCO clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control bit is 2
clock cycles long. The active low reset bit occurs 6 CLKs after the transmission of the last bit of PLL frequency
control.
RTC
M
S
B
16 CLK
L
S
B
21 0
128 CLK
22-Bit Fsc Frequency Control
Start
Bit
Reset
Bit
2 CLK
1 CLK
2 CLK
3 CLK
1 CLK
PAL
Switch
44 CLK
Figure 3−14. RTC Timing
3.21 Internal Control Registers
The TVP5150 device is initialized and controlled by a set of internal registers which set all device operating
parameters. Communication between the external controller and the TVP5150 device is through I
2
C.
Table 3−8 shows the summary of these registers. The reserved registers must not be written. However,
reserved bits in the defined registers must be written with 0s. The detailed programming information of each
register is described in the following sections.
Table 3−8. Registers Summary
REGISTER FUNCTION ADDRESS DEFAULT R/W
Video input source selection #1 00h 00h R/W
Analog channel controls 01h 15h R/W
Operation mode controls 02h 00h R/W
Miscellaneous controls 03h 01h R/W
Autoswitch mask 04h 00h R/W
Software reset 05h 00h R/W
Color killer threshold control 06h 10h R/W
Luminance processing control #1 07h 20h R/W
Luminance processing control #2 08h 00h R/W
Brightness control 09h 80h R/W
Color saturation control 0Ah 80h R/W
Hue control 0Bh 00h R/W
Contrast control 0Ch 80h R/W
Outputs and data rates select 0Dh 47h R/W
R = Read only
W = Write only
R/W = Read and write