Datasheet

Functional Description
22
May 2006SLES043A
TVP5150
5
XTAL1
14.318-MHz or
27-MHz Crystal
6
XTAL2
TVP5150
5
XTAL1
6
XTAL2
C
L1
C
L2
14.318-MHz or
27-MHz Clock
R
NOTE: 100-kΩ resistor R is optional
Figure 3−12. Reference Clock Configurations
3.20 Genlock Control (GLCO) and Real-Time Control (RTC)
A Genlock control function is provided to support a standard video encoder to synchronize its internal color
phase DCO for a clean video line and color lock.
The frequency control word of the internal color subcarrier digital control oscillator (DCO) and the subcarrier
phase reset bit are transmitted via terminal 23 (GLCO). The frequency control word is a 23-bit binary number.
The frequency of the DCO can be calculated from the following equation:
dco
ctrl
sclk
F
F
F
=
x
23
2
where F
dco
is the frequency of the DCO, F
ctrl
is the 23-bit DCO frequency control, and F
sclk
is the frequency
of the SCLK.
3.20.1 TVP5150 Genlock Control Interface
A write of 1 to bit 4 of the chrominance control register at I
2
C subaddress 1Ah causes the subcarrier DTO
phase reset bit to be sent on the next scan line on GLCO. The active low reset bit occurs 7 SCLKs after the
transmission of the last bit of DCO frequency control. Upon the transmission of the reset bit, the phase of the
TVP5150 internal subcarrier DCO is reset to zero.
A Genlock slave device can be connected to the GLCO terminal and use the information on GLCO to
synchronize its internal color phase DCO to achieve clean line and color lock.
Figure 3−13 shows the timing diagram of the GLCO mode.
SCLK
GLCO
23-Bit Frequency Control
Start Bit DCO Reset Bit
MSB
>128 SCLK
1 SCLK
7 SCLK23 SCLK
1 SCLK
LSB
22 21
0
Figure 3−13. GLCO Timing