Datasheet

Functional Description
18
May 2006SLES043A
HSYNC
AVID Start
AVID Stop
VBLK Stop
VBLK Start
VSYNC
AVID Cropped
Area
Active Video Area
Figure 3−11. AVID Application
3.17 Embedded Syncs
Standards with embedded syncs insert SAV and EAV codes into the datastream on the rising and falling edges
of AVID. These codes contain the V and F bits which also define vertical timing. F and V are software
programmable and change after SAV but before EAV, so that the new value always appears on EAV first.
Table 3−4 gives the format of the SAV and EAV codes.
H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and
field counter varies depending on the standard.
The P bits are protection bits:
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
Table 3−4. EAV and SAV Sequence
8-BIT DATA
D7 (MSB) D6 D5 D4 D3 D2 D1 D0
Preamble 1 1 1 1 1 1 1 1
Preamble 0 0 0 0 0 0 0 0
Preamble 0 0 0 0 0 0 0 0
Status word 1 F V H P3 P2 P1 P0