Datasheet
Functional Description
12
May 2006SLES043A
Table 3−1. Data Types Supported by the VDP
LINE MODE
REGISTER (D0h−FCh)
BITS [3:0]
SAMPLING
RATE (0Dh)
BIT 7
NAME DESCRIPTION
0000b x x Reserved
0000b x x Reserved
0001b x x Reserved
0001b 1 WST PAL B 6 Teletext, PAL, System B, ITU−R BT.601
0010b x x Reserved
0010b 1 WST PAL C 6 Teletext, PAL, System C, ITU−R BT.601
0011b x x Reserved
0011b 1 WST, NTSC B 6 Teletext, NTSC, System B, ITU−R BT.601
0100b x x Reserved
0100b 1 NABTS, NTSC C 6 Teletext, NTSC, System C, ITU−R BT.601
0101b x x Reserved
0101b 1 NABTS, NTSC D 6 Teletext, NTSC, System D (Japan), ITU−R BT.601
0110b x x Reserved
0110b 1 CC, PAL 6 Closed caption PAL, ITU−R BT.601
0111b x x Reserved
0111b 1 CC, NTSC 6 Closed caption NTSC, ITU−R BT.601
1000b x x Reserved
1000b 1 WSS, PAL 6 Wide-screen signal, PAL, ITU−R BT.601
1001b x x Reserved
1001b 1 WSS, NTSC 6 Wide-screen signal, NTSC, ITU−R BT.601
1010b x x Reserved
1010b 1 VITC, PAL 6 Vertical interval timecode, PAL, ITU−R BT.601
1011b x x Reserved
1011b 1 VITC, NTSC 6 Vertical interval timecode, NTSC, ITU−R BT.601
1100b x x Reserved
1100b 1 VPS, PAL 6 Video program system, PAL, ITU−R BT.601
1101b x x Reserved
1110b x x Reserved
1111b x Active Video Active video/full field
At powerup the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents with
the lookup table (see Section 3.22.54). This is done through port address C3h. Each read from or write to this
address will auto increment an internal counter to the next RAM location. To access the VDP-CRAM, the line
mode registers (D0h−FCh) must be programmed with FFh to avoid a conflict with the internal microprocessor
and the VDP in both writing and reading. Full field mode must also be disabled.
Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode. When
changing modes, the VDP must allow the current transaction to complete through the delays of the VDP before
switching the line mode register contents. It must also complete loading of the line mode registers before the
next line starts processing. The switch pixel number is set through registers CBh and CCh (see Section
3.22.60).
Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h−AFh, both
of which are available through the I
2
C port.