Datasheet

2−51

2.20.65 FIFO Output Control Register

Address CDh

Default 01h

7 6 5 4 3 2 1 0

Reserved Host access enable

This register is programmed to allow I

C access to the FIFO or allowing all VDP data to go out the video port.

Host access enable:

0 = Output FIFO data to the video output Y[9:2]

1 = Allow I

C access to the FIFO data (default)

2.20.66 Full Field Enable Register

Address CFh

Default 00h

7 6 5 4 3 2 1 0

Reserved Full field enable

This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line

mode registers programmed with FFh are sliced with the definition of register FCh. Values other than FFh in the line

mode registers allow a different slice mode for that particular line.

Full field enable:

0 = Disable full field mode (default)

1 = Enable full field mode