Datasheet

2−25
2.20.16 Configuration Shared Pins Register
Address 0Fh
Default 08h
7 6 5 4 3 2 1 0
Reserved LOCK23 Reserved LOCK24B FID/GLCO VSYNC/PALI INTREQ/GPCL/VBLK SCLK/PCLK
LOCK23 (pin 23) function select:
0 = FID (default, if bit 3 is selected to output FID)
1 = Lock indicator (indicates whether the device is locked both horizontally and vertically)
LOCK24B (pin 24) function select:
0 = PALI (default, if bit 2 is selected to output PALI)
1 = Lock indicator (indicates whether the device is locked both horizontally and vertically)
FID/GLCO (pin 23) function select (also refer to register 03h for enhanced functionality):
0 = FID
1 = GLCO (default)
VSYNC/PALI (pin 24) function select (also refer to register 03h for enhanced functionality):
0 = VSYNC (default)
1 = PALI
INTREQ/GPCL/VBLK (pin 27) function select:
0 = INTREQ (default)
1 = GPCL or VBLK depending on bit 7 of register 03h
SCLK/PCLK (pin 9) function select:
0 = SCLK (default)
1 = PCLK (1x pixel clock frequency)
Please see Figure 2−8 for the relationship between the configuration shared pins.
2.20.17 Active Video Cropping Start Pixel MSB Register
Address 11h
Default 00h
7 6 5 4 3 2 1 0
AVID start pixel MSB [7:0]
Active video cropping start pixel MSB [9:2], set this register first before setting register 12h. The TVP5150A decoder
updates the AVID start values only when register 12h is written to. This start pixel value is relative to the default values
of the AVID start pixel.