Datasheet

2−19
Pin 2
4
M
U
X
PALI 0
1
PALI/HLK/HVLK
HLK/HVLK
M
U
X
VSYNC 0
1
VSYNC/PALI/HLK/HVLK
0F(Bit 2)
VSYNC/PALI
Pin 2
3
M
U
X
VLK/HVLK 1
0
GLCO
FID
M
U
X
FID/VLK/HVLK 0
1
FID/GLCO/VLK/HVLK
0F(BIT 3)
FID/GLCO
03(Bit 4)
HVLK
M
U
X
HLK 0
1HVLK
0F(Bit 4)
LOCK24B
M
U
X
HVLK 1
0VLK
0F(BIT 6)
LOCK23
Pin 27
M
U
X
VBLK 1
0
INTREQ
GPCL
M
U
X
VBLK/GPCL 1
0
INTREQ/GPCL//VBLK
03(BIT 7)
VBKO
0F(BIT 1)
INTREQ/GPCL/VBLK
Pin
9
PCLK
M
U
X
SCLK 0
1
PCLK/SCLK
0F(BIT 0)
SCLK/PCLK
Figure 2−8. Configuration Shared Pins
NOTE: Also refer to the configuration shared pins register at subaddress 0Fh.