Datasheet

2−18
2.20.4 Miscellaneous Control Register
Address 03h
Default 01h
7 6 5 4 3 2 1 0
VBKO GPCL pin
GPCL I/O mode
select
Lock status
(HVLK)
YCbCr output
enable (TVPOE)
HSYNC, VSYNC/PALI,
AVID, FID/GLCO
output enable
Vertical blanking
on/off
Clock output
enable
VBKO (pin 27) function select:
0 = GPCL (default)
1 = VBLK
GPCL (data is output based on state of bit 5):
0 = GPCL outputs 0 (default)
1 = GPCL outputs 1
GPCL I/O mode select:
0 = GPCL is input (default)
1 = GPCL is output
Lock status (HVLK) (configured along with register 0Fh, please see Figure 2−8 for the relationship between the
configuration shared pins):
0 = Terminal VSYNC/PALI outputs the PAL indicator (PALI) signal and terminal FID/GLCO outputs the field
ID (FID) signal (default) (if terminals are configured to output PALI and FID in register 0Fh)
1 = Terminal VSYNC/PALI outputs the horizontal lock indicator (HLK) and terminal FID outputs the vertical
lock indicator (VLK) (if terminals are configured to output PALI and FID in register 0Fh)
These are additional functionalities that are provided for ease of use.
YCbCr output enable:
0 = Y(OUT7:0) high impedance (default)
1 = Y(OUT7:0) active
HSYNC, VSYNC/PALI, active video indicator (AVID), and FID/GLCO output enables:
0 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high-impedance (default).
1 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are active.
Vertical blanking on/off:
0 = Vertical blanking (VBLK) off (default)
1 = Vertical blanking (VBLK) on
Clock output enable:
0 = SCLK output is high impedance.
1 = SCLK output is enabled (default).
NOTE: When enabling the outputs, ensure the clock output is not accidently disabled.
Table 2−11. Digital Output Control
Register 03h, Bit 3
(TVPOE)
Register C2h, Bit 2
(VDPOE)
YCbCr Output Notes
0 X High impedance After both YCbCr output enable bits are programmed.
X 0 High impedance After both YCbCr output enable bits are programmed.
1 1 Active After both YCbCr output enable bits are programmed.
NOTE: VDPOE default is 1 and TVPOE default is 0.