Datasheet

2−15
Table 2−9. Registers Summary (Continued)
REGISTER FUNCTION ADDRESS DEFAULT R/W
ROM major version 82h 03h R
ROM minor version 83h 21h R
Vertical line count MSB 84h R
Vertical line count LSB 85h R
Interrupt status register B 86h R
Interrupt active register B 87h R
Status register #1 88h R
Status register #2 89h R
Status register #3 8Ah R
Status register #4 8Bh R
Status register #5 8Ch R
Reserved 8Dh−8Fh
Closed caption data registers 90h−93h R
WSS data registers 94h−99h R
VPS data registers 9Ah−A6h R
VITC data registers A7h−AFh R
VBI FIFO read data B0h R
Teletext filter 1 B1h−B5h 00h R/W
Teletext filter 2 B6h−BAh 00h R/W
Teletext filter enable BBh 00h R/W
Reserved BCh−BFh
Interrupt status register A C0h 00h R/W
Interrupt enable register A C1h 00h R/W
Interrupt configuration C2h 04h R/W
VDP configuration RAM data C3h DCh R/W
Configuration RAM address low byte C4h 0Fh R/W
Configuration RAM address high byte C5h 00h R/W
VDP status register C6h R
FIFO word count C7h R
FIFO interrupt threshold C8h 80h R/W
FIFO reset C9h 00h W
Line number interrupt CAh 00h R/W
Pixel alignment register low byte CBh 59h R/W
Pixel alignment register high byte CCh 03h R/W
FIFO output control CDh 01h R/W
Reserved CEh
Full field enable CFh 00h R/W
Line mode registers
D0h
D1h−FBh
00h
FFh
R/W
Full field mode register FCh 7Fh R/W
Reserved FDh−FFh
R = Read only
W = Write only
R/W = Read and write