Datasheet

2−13
2.17.2 RTC Mode
Figure 2−7 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is 4 times slower than the GLCO
clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control bit is 2 clock cycles long.
The active low reset bit occurs 6 CLKs after the transmission of the last bit of PLL frequency control.
RTC
M
S
B
16 CLK
L
S
B
21 0
128 CLK
22-Bit Fsc Frequency Control
Start
Bit
Reset
Bit
2 CLK
1 CLK
2 CLK
3 CLK
1 CLK
PAL
Switch
44 CLK
Figure 2−7. RTC Timing
2.18 Reset and Power Down
Terminals 8 (RESETB) and 28 (PDN) work together to put the TVP5150A decoder into one of the two modes.
Table 2−8 shows the configuration.
Table 2−8. Reset and Power Down Modes
PDN RESETB CONFIGURATION
0 0 Reserved (unknown state)
0 1 Powers down the decoder
1 0 Resets the decoder
1 1 Normal operation
2.19 Internal Control Registers
The TVP5150A decoder is initialized and controlled by a set of internal registers which set all device operating
parameters. Communication between the external controller and the TVP5150A decoder is through I
2
C. Table 2−9
shows the summary of these registers. The reserved registers must not be written. Reserved bits in the defined
registers must be written with 0s, unless otherwise noted. The detailed programming information of each register is
described in the following sections.